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ADC delivers 150MSps for 3G wireless standards

Posted: 20 Dec 2006 ?? ?Print Version ?Bookmark and Share

Keywords:3G? WiMAX? ADC? TD-SCDMA? ADI?

AD9640 ADC from ADI

Analog Devices Inc. (ADI) has introduced a dual 14bit ADC said to be the first to achieve sampling rates of 150MSps. Supporting all 3G base station wireless standards, including W-CDMA, CDMA2000 and TD-SCDMA, ADI said the AD9640 is the only dual 14bit ADC that samples at rates beyond 135MSps, a common requirement for the emerging WiMAX.

Prior to the AD9640, sampling rates beyond 135MSps could only be realized by using single-channel ADCs. With the AD9640, base station designers are able to reach higher sampling rates with one dual ADC, enabling a 50 percent reduction in board space requirements. Additionally, the AD9640 simplifies the design of multicarrier wireless infrastructure systems by decreasing the amount of analog filtering in front of the ADC and offering low power consumption, the company explained.

Multiple 3G standards
"Today's base station manufacturers are faced with designing for a variety of 3G wireless standards, as well as the emerging WiMAX standard, while also focusing on reducing costs," said Kevin Kattmann, product line director, high-speed signal processing group, ADI. "Addressing this challenge, the AD9640 offers the performance and sample rate required for these standards, but also provides the low power, small size and digital features to lower overall system costs."

The new ADC delivers quality performance, while only consuming 390mW of power per channel. The AD9640 offers SNR of 72.7dBFS and spurious free dynamic range (SFDR) of 85dBc with a 70MHz IF, and is also capable of supporting IFs as high as 450MHz, enabling WiMAX designers to use a single downconversion receiver design instead of the traditional two downconversion stages. For optimal performance, the AD9640 can be driven with ADI's AD8352 low-distortion differential amplifier.

The AD9640 divides the input clock by an integer between 1 and 8, reducing system complexity and improving clock jitter. In a traditional base station transmitter, the DACs, such as ADI's AD9779, will have a higher clock rate, which is divided down to match the ADC. By implementing the clock divider on-chip, the AD9640 eliminates the need for an external divider. In addition, the phase noise of the source improves in proportion to the divide ratio.

Reduced system cost
Incorporated on the AD9640 are digital features that reduce system costs by simplifying the automatic gain control (AGC) loop in the receiver. The new converter is said to be the industry's first to integrate digital features including a block that monitors the incoming composite signal power, and indicates whether the gain of the receiver needs to be increased or decreased. While the signal monitor block can act as a slow mechanism to change the receiver gain, the AD9640 also includes fast detect (FD) modes, allowing designers to detect an input overrange condition in as little as two clock cycles, immediately reducing the gain to avoid overdriving the analog front end. In addition to providing clipping information, the FD bits have programmable thresholds that are useful in optimizing the receiver AGC loop.

The AD9640 is sampling today with production quantities available in April 2007. The ADC is available in 12bit and 14bit resolutions with sample rates of 80-, 105-, 125- and 150MSps. CMOS and LVDS output modes are supported. The 14bit ADC is priced between $37.50 and $87.50 and the 12bit ADC is priced between $25.05 and $47.97 in 1,000-piece quantities. Both versions are packaged in 9-by-9mm, 64-lead lead-frame chip-scale package (LFCSP).

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