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IC verification users satisfied, survey says

Posted: 21 Dec 2006 ?? ?Print Version ?Bookmark and Share

Keywords:IC verification? EDA tool? EDA tools? ASIC? SoC?

Sixty percent of chip designers say they are satisfied with their IC verification environments according to a survey, released last week, of more than 600 engineers sponsored by hardware-assisted verification provider Emulation and Verification Engineering (EVE).

Respondents to the survey said that execution speed and ease of use are the parts of the verification flow most in need of improvement. Participants also said they want better block testing and block regression. Most respondents are using hardware/software verification and hardware-assisted verification, and nearly half are using assertion-based verification.

Dino Caporossi, vice president of corporate marketing at EVE, said the company conducted the survey at the Design Automation Conference last July to characterize potential target customers and adjust its marketing plans. He said the survey drew a total of 617 respondents, including 477 when EDA vendor representatives and academics were filtered out. Not all respondents answered every question.

Slightly more than half of the respondents were front-end and back-end designers. Twelve percent were front-end verification engineers, and 8 percent were back-end verification engineers. Others were involved in system design, EDA management, sales and marketing. Most are working with ASICs or SoC.

Asked about approximate size of their latest chip design, 28 percent said under 2 million gates, 25 percent between 2 million and 5 million, 22 percent between 5 million and 10 million, and 15 percent between 10 million and 50 million. Ten percent said their latest design was over 50 million gates.

Sixty percent of 398 respondents said they were satisfied with their IC verification environment, while 40 percent were not. This finding surprised Caporossi. He speculated that respondents, who gave their names, were afraid that a salesperson might call them if they indicated they were unhappy.

But respondents did not appear to hold back on other questions. Asked which part of the verification environment most needs improvement, 25 percent selected execution speed, 21 percent ease of use and 15 percent compile speed.

Asked which part of the verification flow needs the most improvement, 25 percent selected block test.

- Richard Goering
EE Times




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