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Mentor unveils rule decks for TSMC 65nm tech

Posted: 27 Dec 2006 ?? ?Print Version ?Bookmark and Share

Keywords:EDA? Calibre? Mentor Graphics? 65nm? TSMC?

Mentor Graphics Corp. has announced the availability of Calibre xRC and Calibre xL rule decks for TSMC's advanced 65nm process node. These rule decks provide advanced modeling capabilities including process sensitivity, and self and mutual induction models. Calibre now provides a solution for many types of IC designs including analog, digital, mixed signal and memory.

For nanometer designs, accurate simulation and analysis requires more than traditional resistance and capacitance. Designers need a post-layout silicon model that incorporates inductance, process sensitivity effects and efficient accounting of effects not captured in the device model. Using Calibre xRC and Calibre xL in the design flow helps ensure that designers have all the data they need to obtain successful first pass silicon.

"We have developed testing methodology for parasitic extraction tools to make sure we deliver accurate solutions to our customers. Calibre xRC and Calibre xL performed well in our internal tests and offer advanced modeling capabilities to capture process variation effects that are necessary for 65nm," said Ed Wan, senior director of design services marketing, TSMC.

"Delivering accurate, complete parasitic models is an integral part of Calibre's overall objective to improve silicon yield," said Joe Sawicki, VP and general manager, design to silicon division, Mentor Graphics. "When coupled with Calibre LVS for device modeling, Calibre xRC and Calibre xL help designers address parametric yield issues by accurately capturing process variation effects in device and interconnect models. Additionally, customers now have access to a full complement of inductance models with self, mutual and skin effect modeling that is necessary for today's high frequency interconnect."

New nanometer silicon model
Shrinking geometries and increasing design size in the nanometer era have enabled greater functionality on a single chip. But with the increased functionality comes new complexities that create more problems in the attempt to attain design closure. This requires an electrical representation of the chip that accounts for the actual physical design of its devices and interconnect, and accurate silicon model. Calibre xRC and Calibre xL meet the demands of nanometer designs with a comprehensive approach to device and parasitic extraction to compose accurate silicon models enabling a large variety of post-layout analyses.

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