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eASIC expands structured ASIC line with ARM926EJ processor

Posted: 08 Jan 2007 ?? ?Print Version ?Bookmark and Share

Keywords:processor? ASIC? FPGAs? FPGA? ASIC?

eASIC Corp. has added the ARM926EJ processor to its Nextreme 90nm product family. Now, said the company, FPGA, ASIC and SoC designers can benefit from a low-cost, fast-turnaround design with no-minimum order quantity.

Under the agreement signed between ARM and eASIC, this partnership will enable a broad range of users to have access to a 32bit CPU core on a configurable fabric, while meeting the power, price and performance requirements of their Structured ASIC or Platform Designs, according to eASIC.

eASIC implemented the 32bit ARM926EJ processor using its standard design flow and obtained 150MHz typical performance. The 90nm Nextreme family with the embedded ARM926EJ processor is available now and is well suited for use in a vast range of applications, including digital imaging, portable media players, wired communication, wireless communication, storage and industrial. A development board is available for customers use.

"eASIC's Structured ASIC product enables the ARM926EJ processor to be made available in a configurable fabric for mass usage," said Mark Brass, vice president pperations, Physical IP. "This offering can significantly broaden the users' community of this processor, by eliminating the mask cost and allowing any volume production required, eASIC opens the opportunity to extend this product offering to a wide range of applications and emerging markets."

Nextreme devices
The 90nm Nextreme devices offer a powerful combination of fast turnaround prototypes to quickly verify designs together with low-cost production devices for high-volume applications. Prototypes can be manufactured as fast as 3 weeks, using mask-less Direct-write eBeam and there is no mask charge and no minimum order quantity. The Nextreme features include system performance of up to 350MHz, densities ranging from 350K gates to 5 million ASIC gates and up to 790 user I/Os.

"eASIC is building a wide and deep IP portfolio to offer its customers the low-cost, flexibility and time-to-market advantages of design-reuse, and the ARM926EJ processor is a major milestone in this roadmap," said eASIC CEO Ronnie Vasishta. "Our goal is to provide our customers with an affordable solution for implementing their own innovative products cost-effectively and with the ability to quickly react to market fluctuation. The digital consumer market, which is a major industry growth driver, dictates the need to reduce cost, shorten turnaround time and embrace flexibility. These benefits are made possible using a mask-less lithography, such as employed for our Nextreme fabric, and offering design reuse capabilities such as the ARM processor. We are eager to provide our customers with this very valuable yet cheap silicon real-estate."

The ARM926EJ processor features a Jazelle technology-enhanced 32bit RISC CPU, flexible size instruction and data caches, tightly coupled memory interfaces, memory management unit. It also provides separate instruction and data AMBA AHBTM interfaces particularly suitable for Multi-layer AHB-based systems. The ARM926EJ processor implements the ARMv5TEJ instruction set and includes an enhanced 16 x 32-bit multiplier, capable of single cycle MAC operations. This ARMv5TEJ instruction set includes 16-bit fixed point DSP instructions to enhance performance of many signal processing algorithms and applications as well as supporting Thumb and Java byte code execution.

- Marty Gold

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