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Verilog simulator offers faster RTL, gate-level simulation

Posted: 09 Jan 2007 ?? ?Print Version ?Bookmark and Share

Keywords:debugging tools? debuggers? debugger? simulator? simulators?

Graphical debugging tool provider SynaptiCAD has released VeriLogger Extreme, a compiled-code Verilog 2001 simulator. Priced at $4,000 on Windows platforms, it's a step towards greater things, according to the company.

"VeriLogger Extreme is SynaptiCAD's first step to releasing a fully compliant SystemVerilog simulator," said Dan Notestein, president of SynaptiCAD. "The new architecture is C++ based, allowing us easily to support object-oriented SystemVerilog features such as polymorphism very rapidly and naturally. This architecture also makes for simpler integration with SystemC simulations."

Notestein said that the first release supports the entire Verilog 2001 standard, and that over the next few months the company will release selected SystemVerilog capabilities.

Compared to SynaptiCAD's existing VeriLogger Pro interpreted Verilog simulator, VeriLogger Extreme claims to run 8 times faster for RTL simulation and 30 times faster for gate-level simulation. It also claims to use 20 percent less memory.

VeriLogger Extreme comes bundled with SynaptiCAD's graphical BugHunter Pro Verilog/VHDL debugging environment, which supports all major Verilog simulators. BugHunter provides source-level debugging, a waveform compression engine, and graphical testbench generation features. It also supports importing and exporting simulation test vectors to Agilent and Tektronix pattern generators.

VeriLogger Extreme claims to support all major ASIC and FPGA vendors, including Actel, Altera, Atmel, LSI Logic, Quicklogic and Xilinx. It's available on Linux Solaris, and Windows platforms. Existing VeriLogger Pro customers on maintenance can upgrade for free.

- Richard Goering
EE Times




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