Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Tool claims breakthrough in ASIC debugging

Posted: 10 Jan 2007 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? ASIC? EDA? Synplicity? debugger?

Claiming a breakthrough in ASIC debugging, Synplicity Inc. this week will release details about TotalRecall, which it says will bring full debug visibility to FPGA prototypes used for ASIC verification. If successful, the technology could help FPGA prototypes rival far more expensive emulation systems.

No products use TotalRecall yet, but it has such potential that Synplicity decided to publicly disclose the technology before bringing it to market, said senior marketing director John Gallagher. The company promises that TotalRecall will capture all signals within a design, including memory states, for a user-defined number of cycles before an error occurs. It then generates a testbench that can be exported to HDL simulators.

New FPGA prototyping era
As such, TotalRecall could open a new era for FPGA prototyping systems, which are extremely fast and cheap but are hobbled by a lack of debugging visibility. For this reason, Gallagher noted, many design teams use FPGA prototypes for their initial ASIC verification work, but turn to an emulator when they need full-signal visibility. Emulators today can cost more than $1 million.

"If we can gain full-signal visibility over a period of time, then we can equal what an emulator can do, and up it with 50 to 100 times faster speeds," Gallagher said. "This really brings emulation to the masses. It brings cost and performance to a whole different trade-off."

While Synplicity is best known for its FPGA synthesis tools, TotalRecall isn't its first foray into ASIC verification. The company's Certify product supports ASIC verification by partitioning netlists into FPGA prototyping systems. TotalRecall technology doesn't require Certify, but will probably become part of an automated flow within Certify, Gallagher said.

The technology behind TotalRecall has its roots in Bridges2Silicon, a debugging company Synplicity bought four years ago. An internal development effort followed that acquisition.

TotalRecall will go into beta sites during the next two or three months, Gallagher said, but there's no timetable yet for product introductions.

TotalRecall "is a different idea and one that looks promising," said Gary Smith, chief analyst at Gary Smith EDA. "I think it's significant not only because we need debuggers right now, but because it says that Synplicity is no longer just an FPGA house."

Replicating logic
Gallagher noted that TotalRecall can detect when a bug occurs, run backwards in time to examine the conditions that led to it and provide a detailed testbench for the simulator. To do so, it essentially synthesizes an additional copy of the ASIC within the FPGA prototyping system. This replicated design runs backwards in time for the number of cycles requested by the user.

TotalRecall examines bug conditions

TotalRecall can also synthesize assertions into the replicated hardware, Gallagher noted. This supports assertion-based verification at the high speeds allowed by FPGA prototypes. The initial support is for Open Verification Library assertions. Synplicity is also developing a Property Specification Language compiler, but that's a major development that will take some time, Gallagher noted.

Gallagher said Synplicity expects that TotalRecall will support all commonly used HDL simulators. Further, Synplicity intends for it to be integrated with a variety of FPGA prototyping platforms, including those from members of Synplicity's Partners in Prototyping program. They include Altera, AMO, ARM, Dini Group, EVE, Flexody, Gidel, Hardi Electronics, Nallatech, ProDesign and SK-Electronics.

- Richard Goering
EE Times




Article Comments - Tool claims breakthrough in ASIC deb...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top