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Power efficiency impacts chip design

Posted: 12 Jan 2007 ?? ?Print Version ?Bookmark and Share

Keywords:chip design? power consumption? VLSI Conference 2007? Mark Horowitz? semiconductor?

Power consumption is a compelling force that affects IC design today. It is the primary limiter of a chip's performance.

Prof. Mark Horowitz presented his research findings on this topic in a plenary session during the recent VLSI Conference 2007 in Bangalore. Horowitz is professor and director of the computer systems lab, Stanford University, and Rambus Inc.

"Previously, the power consumed by a functionfor instance, a processorshrunk in relationship with the size. So, if you filled up the same die area, the power would remain roughly the same," Horowitz explained to EE Times-India shortly after his talk. "However, today, if you fill up the die again the same way, it will consume more power, as the total power is not shrinking as fast as the size."

Today's design approaches have to look at the problem from a performance efficiency perspective. The goal of design is to maximize the performance for a given amount of power.

"Designers used to focus on high performance systems. Now, they have to worry about not just what the performance is, but what is the energy cost of getting that performance. They have to choose solutions that have very good power efficiency," Horowitz added.

Although there may be many possible directions that one can look at for achieving power efficiency, Horowitz shared that the approach to energy efficiency will probably take the form of some level of domain optimization. "The right solution for wireless or signal processing in the front-end of a wireless system might be different from that for the graphics or the user interface. I think we will see some domain specialization."

Designing power-efficient chips will also require design engineers to be adept at all levels. "If you do something at the architectural level, you will actually have to know the implementation implicationsto know how good the architecture is. I think there will be a lot of coupling between these."

Designers will also have to maintain a relationship between leakage power and dynamic power. "Lower leakage energy will degrade your performance. Hence, to acquire the same performance, you have to increase your power supply, which will increase in turn your dynamic power," Horowitz explained. "People have demonstrated that in optimal designs, the leakage energy should be about 40 to 50 percent of the dynamic power."

With product features increasing faster than the reduction of power consumption, finding the right approach to shrink a gate's average power will be imperative for designers. "You could do that by either slowing down the gate or by running only one or a few of the many blocks on a chip. However, this would mean that most of the gates will not be running all the time," Horowitz said.

- Krishnan Sivaramakrishnan
EE Times India

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