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Benefits of thermally aware design

Posted: 16 Jan 2007 ?? ?Print Version ?Bookmark and Share

Keywords:thermally-aware design? dealing with leakage power? process and design technologies? chip design? Rajit Chandra?

Advances in process and design technologies pose significant challenges when chips are being designed to meet often-conflicting specifications. Today, power dissipation is the dominant performance-limiting factor in nanometer designs. Materials and structures used in nanometer processes show increased leakage power and decreased thermal conduction.

The net result of these effects is a marked increase in power and temperature variations across the die. Corner-analysis methods that assume a uniform chip temperature are no longer adequate for successful design closure.

Temperature variations across the die can affect chip power, speed and reliability. Leakage power, in particular, is exponentially dependent on temperature, and if handled improperly, can result in thermal runaway. Performance factors such as voltage drop and clock skew are susceptible to spatial temperature variations and can result in performance degradation.

Temperature also plays a major role in device performance degradation due to phenomena such as bias temperature instability, especially in analog circuits. And finally, the cooling effectiveness of packages and associated cooling systems can be reduced by the presence of hot spots on the die. In many cases, on-chip thermal sensors need to be located in areas of maximum temperature.

These tips for thermally aware design will improve the accuracy of current design tools and flows by including the distribution of temperature on the die.

Do

  • Run thermal analysis as early as possible to detect and eliminate hot spots in the design. Physical layout and power distribution profiles are known as early as the floorplanning stage, which is also a good time to incorporate early thermal planning.

  • Incorporate the effect of package and metallization when developing a thermal picture of the die. Ignoring these structures, and using power or power-density profiles to estimate temperature may result in gross inaccuracies in power estimation and other temperature-sensitive analyses.

  • Check for thermal effects at every design iteration that might change the power profile of the chip. Thermal analysis at a few key operating modes of the device is often sufficient to provide good feedback on hot spots and other concerns.

  • Use distributed temperature information in the design of clock trees and critical nets that are sensitive to on-chip variation. Timing and signal-integrity analyses also benefit from accurate temperature and voltage-drop information.

  • Design thermal-management systems, such as on-chip thermal sensors, with a good thermal picture of the die. If the sensors are placed incorrectly, they may not capture the die's maximum temperature and may provide optimistic feedback.

Don't

  • Calculate the maximum temperature of the die using a single power value and a single Qja value of the package. This temperature value is usually optimistic and does not capture the effect of hot spots on the die.

  • Estimate power and IR drop without considering local temperature variation. Leakage power, which is a dominant component of the total power, is exponentially dependent on temperature and can vary significantly with small changes in temperature. This power variation can also cause significant variation in the voltage drop along the power rails.

  • Use corner analyses, which assume single, uniform chip temperatures, for checking the timing performance of the chip. Temperature differences of more than 10C, coupled with the aforementioned variation in voltage drop, can result in significant changes in cell delays. Additionally, the increasing effect of delay inversion can cause problems with setup-time analyses.

  • Run reliability analysis without considering the temperature variation along metal interconnects. The mean time-to-failure for wires is exponentially dependent on temperature and can result in optimistic designs that may fail prematurely in the field.

  • Design chip packages without checking the presence and magnitude of hot spots on the die. Hot spots severely erode the effectiveness of cooling material and can result in higher operating temperatures of the device.

- Rajit Chandra
Founder and CTO, Gradient Design Automation Inc.




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