Macronix reworks SONOS for next-gen flash

Macronix International is working on a flash memory structure that it believes will dismantle the barriers expected to confront today's floating-gate technology at the 45nm node.

Macronix's BE-SONOS is a bandgap-engineered variation of the silicon-oxide-nitride-oxide-silicon (SONOS) formula. SONOS has been around for years and is seen as a better means for embedding flash than the typical floating-gate structure.

Allen Yu, a researcher at the Macronix Technology Development Center, said the company will produce a 2Gbit test chip next year using 75nm technology. He thinks commercialization will take place at 45nm—around 2010—once floating-gate NAND has reached its scaling limits. Macronix plans to manufacture chips as well as license the technology.

Leakage problems
Because the SONOS structure is compatible with a generic logic process, it could help push embedded flash into applications long considered out of bounds because of cost. But leakage problems afflict conventional SONOS. In most cases, the first oxide layer is too thin to prevent tunneling.

Researchers have previously responded by adding another nitride layer, bumping up the total thickness to less than 4nm. That has resulted in better retention, but the slower programming time has proved an unacceptable trade-off.

With BE-SONOS, Macronix adds further layers of oxide and nitride. "The innovative part is to replace the tunneling oxide O1 layer in SONOS with O1-N1-O2, so BE-SONOS actually equals a SONONOS structure," Yu said. The result is a thicker dielectric layer, measuring 5.3nm. That is then overlaid with a 7nm nitride layer (N2) that traps the charge. The final layer (O3) is a 9nm-thick blocking oxide.

Because of the total thickness of the first O1-N1-O2 layer, retention is high. But when the device is programmed, band offset effectively eliminates the blocking properties of N1 and O2, allowing the electrons to tunnel easily through the O1 layer.

NAND first
Yu said the structure is suitable for NAND or NOR flash but will probably first be used in NAND. Programming occurs at 6MBps. But erase times are 3ms to 4ms per block, a little higher than the normal 2ms, so fine-tuning continues. Endurance, at 10,000 or more cycles, is on par with today's flash.

Samsung Semiconductor earlier this year introduced a similar structure for its charge-trap flash (CTF) devices. It employs a TANOS structure, comprising tantalum, aluminum oxide, nitride, oxide and silicon layers. TANOS is said to mark the first application of a metal layer coupled with a high-k material in a NAND device.

BE-SONOS is also a charge-trapping device. But "TANOS adopts new materials," said Yu, whereas "BE-SONOS is fully CMOS-compatible."

- Mike Clendenin
EE Times