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Xilinx ISE upgrade shortens FPGA design cycles

Posted: 18 Jan 2007 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? ISE 9.1i? Virtex-5? Spartan-3? Xilinx?

Xilinx Inc. has introduced the 9.1i upgrade of its Integrated Software Environment (ISE) design suite, said to be the most widely used in the industry. This latest release is optimized to meet today's leading design challenges: timing closure, productivity and power.

In addition to 2.5x faster runtimes, ISE 9.1i includes new SmartCompile technology that improves runtimes by up to an additional 6x while maintaining exact design preservation of unchanged logic. The solution optimizes the ExpressFabric technology of its latest 65nm Virtex-5 platform, providing an average of 30 percent faster performance than competing solutions. For power sensitive applications, the design suite also reduces dynamic power by an average of 10 percent.

This technology is facilitated by the efforts of the Xilinx-Synplicity Ultra High-Capacity Timing Closure Task Force, delivering productivity-enhancing capabilities to ensure the fastest path to timing closure and optimize the power and performance of Xilinx Virtex series and Spartan-3 FPGAs.

Increased productivity
Much of the time spent on today's advanced designs is in re-implementing the entire design with each incremental change. These re-implementations take time and introduce the risk of disrupting portions of the design not directly involved with the change. Xilinx SmartCompile technology addresses these issues with the following technologies:

Partitions - Minimize effects of minor changes late in design cycles with cut-and-paste functionality that automatically provides exact preservation of existing placement and routing and reduces time for reimplementation by an average of 2.5x.

SmartGuide - Reduces time for re-implementation by an average of 2X for small changes by leveraging prior implementation results.

SmartPreview - Enables users to pause and resume the place-and-route process and save intermediate results to evaluate the state of their designs. By previewing implementation information such as routing status and timing results, users can make important trade-off decisions without waiting for complete implementation.

SmartCompile technology delivers an order of magnitude increase in productivity as a result of up to a 6x runtime improvement, exact preservation of partitions and improved visibility into the implementation. These improvements are in addition to the 2.5x faster runtimes for challenging designs.

ISE 9.1i also addresses the increasing sophistication of FPGA designers with a number of user interface enhancements including Tcl command console to easily transition from the ISE graphical user interface to a command line environment; and, source code compatibility function that identifies the files necessary to recreate results, which can be imported and exported for source control.

Faster timing closure
New features in ISE 9.1i design tools build on capabilities of ISE Fmax technology, especially designed to deliver unparalleled performance and timing closure results for high-density, high-performance Virtex-5-based designs. The ISE 9.1i integrated timing closure flow incorporates enhanced physical synthesis optimizations that provide higher quality of results. Optimized routing algorithms provide the most efficient utilization of the diagonally symmetric interconnect of the 65nm ExpressFabric technology to minimize delay and fully leverage the high performance features of the Virtex-5 platform.

"Timing closure is the number one issue for FPGA designers, and this release greatly simplifies and accelerates that process," said Bruce Talley, VP of design software division at Xilinx. "Our ISE SmartCompile technology addresses the top challenges facing designers today, allowing designers to reach their performance goals in much less time with fewer, more efficient design iterations. What is just as compelling to our users is that ISE 9.1i also enables them to optimize for low power design requirements without compromises in overall performance."

Underlying the entire ISE 9.1i infrastructure is an expanded timing closure environment?a virtual "timing closure cockpit" that enables intuitive cross-probing between constraint entry, timing analysis, floorplanning and report views so designers can more easily analyze timing problems. The ISE 9.1i integrated timing closure flow incorporates enhanced physical synthesis with improved timing correlation between synthesis and placement timing, resulting in higher quality of results.

Power optimization
New power optimization in Xilinx Synthesis Technology (XST) and placement together with improvements in routing deliver an average of 10 percent lower dynamic power for Spartan-3 FPGAs. XST provides power-aware logic optimizations for macro processing on blocks such as multipliers, adders and BRAMs. Implementation algorithms deploy power-efficient placement strategies and lower capacitance nets within the device to minimize power without sacrificing performance.

ISE Foundation 9.1i suite is immediately available with prices starting at $2,495. A full-featured 60-day evaluation version is available at no charge. All versions of ISE 9.1i software packages support Windows 2000 and Windows XP Professional and Linux Red Hat Enterprise 3.0 and 4.0. ISE Foundation also supports Solaris 2.8 and 2.9.

ISE software delivers programmable logic design solutions to over 300,000 users worldwide with an intuitive, front-to-back design environment for all Xilinx product families, including Virtex-II, Virtex-II Pro, Virtex-4 and Virtex-5 Platform FPGAs, Spartan-3 Generation FPGAs and CoolRunner-II CPLDs.




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