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Spansion develops 'first' 4bit-per-cell flash

Posted: 26 Jan 2007 ?? ?Print Version ?Bookmark and Share

Keywords:flash memory? GPS? MirrorBit? Spansion? Saifun?

After nearly five years of development, Spansion Inc. is pushing its 4bit-per-cell MirrorBit flash memory into production this quarter with densities ranging from 256Mbit to 2Gbit.

The first batch of MirrorBit Quad chips will use a 90nm process at Spansion's Fab 25 and will be drop-in compatible with other industry-standard NAND products, the company said.

Later this year, Spansion will reveal plans for 65nm-based products that will target removable applications such as digital film, MP3, game cartridges and USB flash drives. Spansion also wants to promote MirrorBit Quad for embedded applications, such as e-books and GPS navigation systems.

"Spansion's first generation of 4bit-per-cell devices are suitable for low cost, read-intensive storage applications," said Greg Wong, a flash analyst at Web-Feet Research. "In order to expand into the broader storage market occupied by NAND, Spansion intends to expand device densities and increase performance in subsequent generations."

If MirrorBit gains traction, the 4bit technology could spell trouble for Intel Corp. in the market for high-density data-storage flash devices for third-generation wireless phones. Intel pioneered 2bit-per-cell flash technology with its StrataFlash line, introduced in 1997.

Spansion teamed with Saifun Semiconductors in 2002 to pursue 4bit technology. The partnership was part of a comprehensive settlement of a lawsuit that Saifun, claiming patent infringement, had filed against AMD and Fujitsu.

Unlike Intel's StrataFlash, which uses four levels of charge to create 2bits per cell, Spansion's MirrorBit Quad requires a combination of multilevel and multibit technologies, putting four levels of charge in each of the two physical bit locations within the cell.

- Mike Clendenin
EE Times

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