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Israeli startup preps multicore processor

Posted: 29 Jan 2007 ?? ?Print Version ?Bookmark and Share

Keywords:processor? multicore? Altera? Plurality? eASIC?

Multicore processor specialist Plurality Ltd is starting to ship evaluation boards and associated development kits for its HyperCore processor, the first designs to emerge from the work on its HyperCore Architecture Line. Commercial 64-core chips are scheduled for Q3 this year.

Plurality, a privately owned company established in 2004 by a group of academic engineers and industrialists in Israel, says its architecture is one of the most scalable general-purpose multicore processors yet announced, and has demonstrated HyperCore blocks reaching up to 256 cores.

The initial design was implemented on an Altera Stratix II-180 FPGA and incorporates sixteen 32bit RISC cores managed by a high flow rate synchronizer/scheduler, sharing a common memory. The FPGA design comprises a 4Mbit data cache, a 2Mbit instruction cache, four 32bit multipliers and four 64bit dividers.

First version
The first version of the device to be made in volume will be done on eASIC's Nextreme 90nm structured ASIC family, with 64 32bit RISC cores running at 150MHz.

"The success of our proof of concept shows that Plurality's unique, patented technology is able to provide the much expected performance promised by parallel processors, while offering the programmability of a serial processor," said Moshe Serfaty, chairman and CEO.

Serfaty demonstrated a simulator of the multicore processors to EE Times Europe at last years's Electronica Exhibition. He said the company is now seeking partners and customers in various industries to exploit the flexibility and programmability of the multicore design.

The FPGA design is now being offered on a PCI/PCIe board, from GiDEL's family of PROC Boards, as an evaluation and development kit. The board contains several configurable add-ons such as video and network interfaces, external I/O and others.

Graphic simulator
Also available is a cycle-accurate graphic simulator for HyperCore Processors of up to 256 cores, which Serfaty maintains represents an extremely powerful development and debugging tool.

The company says its Task Oriented Programming model allows designers to transport applications into a powerful multicore system using tools and a development environment they already are familiar with, and very similar to the ones used to program a serial processor.

The evaluation kit enables compiling, running and debugging the code. Once this is achieved, the code can be seamlessly executed by any of Plurality's multicore configurations, without the need to reprogram applications as core capacity increases.

- John Walko
EE Times Europe




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