Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

SiP lacks EDA tool support

Posted: 29 Jan 2007 ?? ?Print Version ?Bookmark and Share

Keywords:system-in-package? SiP? SoC? EDA tools? Fabless Semiconductor Association?

System-in-package (SiP) may be an increasingly attractive alternative to SoCs, but EDA tool support is sorely lacking, according to user panelists at the Fabless Semiconductor Association (FSA) SiP Conference. And it's not just a matter of point tools, panelists said, but the development of an integrated design flow across ICs, packages and PCBs.

SiPs pack multiple die into an IC package, and may even stack up multiple packages in package-on-package (PoP) or package-in-package (PiP) arrangements. They may also include logic and memory ICs, as well as analog circuitry and embedded passive components. They're attractive for consumer applications such as cell phones because they can potentially speed development times over highly integrated SoCs.

But SiPs require a new approach to design, said Matthew Kaufmann, director of IC assembly and package development at Broadcom Corp. He noted that IC design, package design, and pc-board design are all discrete disciplinesand that has to change.

"SiP represents the convergence of IC, package, and PCB design, and all these things need to be integrated together," Kaufmann said. "You will now have to take on things that are beyond the traditional scope you've worked on. Tool capabilities will have to integrate all these concepts."

Packaging is the "poor stepchild" of the electronics industry, Kaufmann said, with no consistent tool set that allows integrated design and analysis. Current tools come from a "PCB mentality" and primarily focus on layout, he said. Handoffs between design domains are "quasi-static," and hard-coded rules don't work for SiP interconnect. In addition to layout, Kaufman said, there's a need for analysis of thermal, electrical, manufacturability, process, and quality characteristics.

Meanwhile, Infineon is working with complex, high-pin count SiPs that require IC/package/PCB co-design, said Jochen Reisinger, director of Infineon's co-design project. "It is very important that the early design work be done with the same flow and tools," he said. "It doesn't make sense to do some paperwork, throw it away, and then go into system, package or IC execution."

Current gaps in the SiP tool flow, Reisinger said, include multi-level constraint management, multi-technology tool support, 3D standard exchange formats, multi-level simulation support, multi-level models, mixed-level verification, and connectivity support. While board designers use IBIS models, he noted, they don't allow one to execute a system simulation with transistor effects.

A standard data format between IC, package and pc-board design tools would greatly help, Reisinger said. "We are putting huge efforts into driving standards to get common data interchange formats," he said. Also needed, he said, is consistent constraint management across all three domains.

But many design tool capabilities are needed, Chen said. For shorter time to market, these include leverage of existing components and real-time interactive design methodologies. For smaller form factors, there's a need for thermal/mechanical simulation, as well as new tools to support emerging through-silicon-via (TSV) technologies. For better performance, Chen said, EDA tools must support high-speed designs and offer electrical modeling capabilities.

Sandisk uses stacked-die SiP for memory ASICs, and uses PoP and PiP for selected products, said Hem Taklar, vice president of assembly and packaging engineering at Sandisk. He noted that designers face many challengeschoosing the best technology and materials, determining a cost-effective layout, evaluating interconnect methods such as wirebond and flip-chip, running electrical analyses, and in Sandisk's case, juggling multiple teams spread across the world.

David Cheskis, technical marketing director at Jazz Semiconductor, noted that many SiPs are driven by analog and mixed-signal applications. They require a combination of advanced design tools, assembly techniques, and IC technology for mixed-signal applications, he said.

One key, Cheskis said, is accurate models, including models for embedded passive components such as resistors, inductors and capacitors. "We need tools to model and integrate these into SiP design," he said. Cheskis said that mixed-signal SiPs require capabilities not found in the digital design world, including transistor-level simulation, thermal and electromagnetic simulation, and an ability to simulate multiple technologies concurrently.

Flynn Carson, director of engineering for emerging technologies at StatsChipPac, presented an assembly subcontractor's point of view. "There's a need for us to become involved with design at the chip level, and get input from chip designers," he said. "Chip designers must consider physical layout and test during design, and they really need to consider signal-integrity and thermal performance."

The current design flow is "pretty static," he said. StatsChipPac takes customer netlists and schematics, runs its own electrical and thermal analyses, and has various levels of customer signoff. "There needs to be a lot of streamlining because the process takes too long," he said. "There are potential mistakes, because it's a very manual process. We need more collaborative tools and real-time design integration."

- Richard Goering
EE Times

Article Comments - SiP lacks EDA tool support
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top