Sematech unveils solution for high-k CMOS devices

In its quest for developing dual metal gates for high-k CMOS devices, chip-making R&D consortium Sematech has demonstrated high-k/metal gate stacks to build high-performance nMOS and pMOS transistors in CMOS configuration.

The solution enhances the commercial implementation of high-k metal gate stacks in transistors for 45nm and 32nm nodes. The technology is also touted to complement the consortium's identification last year of effective nMOS materials for metal gates and previous development of high mobility high-k dielectrics.

The pMOS and nMOS materials were integrated into highly-scaled CMOS devices with low threshold voltage similar to conventional polysilicon/SiO₂ devices and ultrathin equivalent oxide thickness ranging from 1-1.2nm.

The CMOS devices were fabricated with conventional gate-first, high-temperature processing flows, with no reduction to drive currents or other performance metrics. Moreover, no substrate counter-doping or other complicated measures were used for the demonstration.