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Tundra division rolls out Interlaken IP core

Posted: 31 Jan 2007 ?? ?Print Version ?Bookmark and Share

Keywords:IP core? Interlaken? SLE? Tundra? Cortina?

Silicon Logic Engineering Inc. (SLE), a division of Tundra Semiconductor Corp., has announced the development of a licensable Interlaken protocol IP core for use in ASIC or FPGA designs.

SLE's Interlaken IP core is scalable, with early versions providing from 10Gbps to 60+Gbps bandwidth across the interface. Future versions will provide over 120Gbps of bandwidth. This scalability suits Interlaken for multiple generations of future network switches, routers and storage equipment. The scalability is achieved through the combination of the Serdes speed (3.125Gbps to 6.375Gbps) and a variable number of Serdes lanes (1 to 24).

Designed and tested to be easily synthesizable into many ASIC and FPGA technologies, SLE's Interlaken IP core was uniquely built to work with off-the-shelf Serdes from most leading technology vendors. Using the vendor-specific Serdes allows SLE customers to quickly integrate the Interlaken IP core into the customer's technology of choice.

The open Interlaken specification was co-written by Cortina Systems and Cisco Systems to provide a more scalable chip-to-chip interface protocol than previous protocols. Interlaken combines the advantages of the popular SPI4.2 and XAUI interfaces by building on the channelization and per channel flow control features of SPI4.2, and reducing the number of chip I/O pins by using high speed Serdes technology, similar to XAUI.

The SLE licensable Interlaken IP is available through SLE's sales network.




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