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Sematech, TEL advance work on 3D interconnects

Posted: 31 Jan 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Sematech? TEL? 3D interconnect technology?

Sematech and Tokyo Electron Ltd (TEL) entered into a multi-year joint development program to improve the use of 3D interconnect technology and high mobility channel materials in advance manufacturing. Sematech and TEL engineers will collaborate on two separate projectsfirst, a three-year effort to transcend the barriers to 3D processing in volume manufacturing, and then a two-year project to advance the feasibility of using SiGe in transistor gate stacks to increase processing speed.

"Technical engagement with key industry suppliers has long been a core strategy of Sematech," said Giang Dao, vice president and COO of Sematech's advanced technologies division. "TEL has been a valued partner for many years, and we're delighted with this opportunity to take our relationship to a new level as we launch two new advanced technology R&D programs."

Masayuki Tomoyasu, director of development and planning and chief engineer at TEL, added, "We are excited by this opportunity to join TEL's engineering expertise with Sematech's R&D capabilities and know-how to develop leading-edge 3D and epitaxial capability for our semiconductor customers."

Twofold initiative
Under the 3D program, Sematech and TEL will work on early development challenges, including cost-of-ownership modeling, process benchmarking, establishing standards, technology road mapping, and the formation of through-wafer silicon vias. In this connection, TEL will tap into its extensive Si-etch experience for high aspect ratio, high-rate etch development capability at its R&D labs in Japan.

Meanwhile, TEL will be upgrading an existing low-k dielectric etch tool in ATDF, Sematech's subsidiary R&D fab. The upgrade will introduce flexibility in understanding the etching of porous low-k materials and improve the process uniformity and capability of the chamber. These activities will support development of low-k materials for 45nm and 32nm technology generations.

"3D technology offers the prospects of improved performance and functionality, reduced power and chip area, reduced development costs, and faster time to market over conventional, two-dimensional designs," said Sitaram Arkalgud, Sematech's interconnect director. "3D also could allow chip-makers to heterogeneously integrate incompatible fabrication technologies into a single stacked system. However, all sections of the industry must come together to address the availability of the proper infrastructure. We are excited to have TEL as a key partner as we increase the scope of our 3D program."

The second program will draw on Sematech's Front-end Processes (FEP) and TEL engineers to pioneer the use of alternative epitaxial materials in transistor channels. Engineers from both companies will jointly develop processes to integrate such materials with high-k metal gates on advanced short channel devices.

"This work will bring significant benefits to our members by refining our processes on epitaxial channels," said Raj Jammy, SEMATECH FEP director. "It allows us to develop new industry standard and manufacturing friendly processes that can benefit member companies while giving us better insights into the technology."




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