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Cadence deploys CPF in low-power design flow

Posted: 01 Feb 2007 ?? ?Print Version ?Bookmark and Share

Keywords:CPF? Cadence? Si2? Accellera? UPF?

Cadence Design Systems Inc. has added the Common power format (CPF) to its existing logic design, verification and implementation tools. This marks the first deployment of CPF, the format that's at the heart of a controversial standards effort and that now forms the basis of low power solution, Cadence's complete design flow for low-power ICs.

Rather than making CPF available as a feature in tools that would have to be purchased separately, Cadence has made most of its existing digital IC design and verification tools CPF-compliant. It is these tools that now make up the Low Power Solution flow.

Turning point
"This is a big turning point for us," said Eric Filseth, corporate VP of marketing. "We really wanted to have a system where you could capture the power architecture and strategy for your chip just once, at the very beginning of the design flow, and have the entire system, from front to back, honor that and do all the right things with it."

CPF was developed internally by Cadence, a fact at the core of its contentious history. CPF lets designers express power intent and constraints, specifying requirements for such things as power shutoff, multiple supply voltages and state-retention power gating. With CPF, for instance, a designer can define which shutdown sequences should be initiated at different clock edges. Today, that's all done on an ad hoc basis with little or no consistency between tools. "There's a huge amount of manual work involved and the tool environment has been very fragmented," Filseth said.

The Low Power Solution design flow involved more than getting tools to read and write CPF, Filseth said. "There's a much larger effort in making sure that the software does what it's supposed to do, that the router puts wires in the right power domain, that synthesis synthesizes correctly," he said. That's why the new flow involved a two-year effort spread over 11 different engineering groups.

Until now, Filseth said, Cadence customers have managed low-power design by writing their own TCL script extensions, while utilities translated from one tool to the next. Commands were inconsistent between tools. "That's how the industry works right now," he said.

Power format controversy
Cadence introduced CPF last May. Controversy ensued when Cadence's primary EDA rivals felt left out of the format's development process. In consequence, a coalition of companies launched the rival Accellera Unified Power Format (UPF) effort. Today, CPF is owned by the Silicon Integration Initiative (Si2), which recently approved CPF as a specification. Si2 and Accellera representatives say they will try to "converge" the CPF and UPF formats.

Designers using Cadence's tools need no longer worry about the dispute, Filseth said. "Wherever the industry takes CPF and UPF, if the users want it, we'll do it," he said. "If you're a Cadence customer, as of now, the power standards thing is over. Go make chips. Whether it's CPF or UPF or some common thing in the future doesn't matter any more. We've got the software system that will build the chips, and we'll follow wherever the standard goes."

CPF spans tools

As of this week, CPF is supported by most of Cadence's digital IC tools, including, on the verification side, Incisive Design Team and Incisive Enterprise simulators. They're now said to do accurate functional verification of power shutoff, including power-down and power-up sequences. With the Incisive Design Team manager, Cadence says, users can specify power intent directly in the verification plan.

CPF support is not yet available for Cadence's Incisive Formal Verifier or logic emulation products, but this will come in the future, Filseth said.

What-if explorations
On the implementation side, the Encounter RTL Compiler supports CPF, and lets designers conduct what-if explorations to understand the tradeoffs of different power-management techniques. Encounter Test can read CPF power intent to create distinct test modes for power domain and power shutoff requirements.

In the SoC Encounter System for IC physical design, the power intent read through CPF can be used to set up power domains, and to insert level shifters and isolation cells alongside the standard-cell placement. A power switch insertion command is available for power shutoff designs. Finally, Cadence's VoltageStorm power verification product uses CPF to help designers verify the power grid.

As of today, however, CPF only works from the register-transfer level on down. Chi-Ping Hsu, chief strategist of product and technology for Cadence, said there's discussion about extending CPF to analog, silicon package and system-level design.

The Low Power Solution announcement closely follows Cadence's donation to Si2 of source code for a CPF version 1.0 parser. The CPF 1.0 specification is currently available to members of Si2's Low Power Coalition, and will be available to the public after a 60-day patent exclusionary period closes on March 3.

- Richard Goering

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