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High-speed interconnects reshape board

Posted: 01 Feb 2007 ?? ?Print Version ?Bookmark and Share

Keywords:interconnect? PCIe? RapidIO? Scalable System Packet Interface? Rick Merritt?

Cox: A standards body must weigh in on 6.25Gbps.

A handful of high-speed interconnects are driving changes in how designers handle fast signals.

The Scalable System Packet Interface (SPI-S) from the Optical Internetworking Forum (OIF) aims to carry data at 6Gbps and up between chips or boards in a communications system.

The PCI Special Interest Group was set to finish the spec for PCIe 2.0 last December, which uses a native 5GHz signaling rate. And the RapidIO Trade Association has been touring the United States and Asia to discuss its 2.0 spec for interconnects, running at up to 6.25Gbps.

While the technologies target a variety of sometimes-overlapping tasks in communication and computer systems, all will become options in the board designer's tool chest. At the same time, the move to higher data rates will demand new techniques in interconnect design, especially signal integrity.

"Five and 6.25Gbps are not the urgent need of the industry today, but the technology is available and definition by a standards body is important before a de facto choice just happens," remarked Tom Cox, executive director of the RapidIO group.

SPI-S arrives at a time when communications giant Cisco Systems Inc. is well down the road to making an internally developed protocol called Interlaken, a staple in the many ASICs it designs for its systems. Known within Cisco as "Spaui"because it's a combination of the existing SPI 4.2 interconnect and Xaui, a 10GbE linkInterlaken will appear on at least a dozen of the 15 or so ASICs in the works at Cisco's storage-networking group alone.

Cisco co-developed the interface with Cortina Systems Inc. and announced last April that Cortina would make it available as a royalty-free download. Like SPI-S, Interlaken rides on top of the OIF's Common Electrical Interface (CEI) as a physical transport.

SPI-S is an attempt by the OIF to deliver a protocol that has gone through its formal standards process. Like Interlaken, it is independent of any physical transport but is designed to ride on the short- and long-reach versions of CEI, currently defined at 6Gbps and 11Gbps.

Future-proof protocol
Both protocols act as upgrades to the existing SPI 4.2 link. SPI 4.2 defined both protocol and PHY and was thus fixed as 16 600Mbps to 900Mbps channels. By contrast, SPI-S or Interlaken could ride on any future higher-speed physical interconnect.

SPI-S typically links framer and packet processing chips in a comms system.

Both SPI-S and Interlaken are aimed at linking traffic-framing and network-processing chips on a single card or over a backplane at speeds faster than SPI 4.2. The streaming semantics of the OIF interconnects are geared for fast and reliable packet handling in a communications system.

By contrast, PCIe and RapidIO both implement a more CPU-centric model based on DMA, said Brian Holden, co-chair of the OIF's marketing group and a principal engineer at PMC-Sierra Inc. In the event of a system failure, the SPI links tend to automatically re-establish a connection. By contrast, interconnects based on DMA tend to require a manual reboot after a system failure, Holden said.

The 5GHz PCIe 2.0 is indeed mainly geared for computers. It is expected to be used first for bandwidth-hungry graphics and later for server and storage applications. However, because PCIe 1.0 is becoming so popular based on high-volume use in PCs, the new version could see a big uptake in embedded and communications systems as a low-cost option in the future.

A companion electromechanical spec defining eye diagrams and compatibility is still in a version 0.7 draft stage but should be done by June. Compliance and interoperability tests for PCIe 2.0 are expected to roll out by the end of 2007, with products ramping in 2008.

Serial RapidIO, which will support 5Gbps and 6.25Gbps transmissions, has yet to come to a final ballot in the trade group. The association has been presenting details of the spec to engineers in a road show across the United States, Japan, China and India.

At 6Gbps, SPI-S is next in a wave of speedy interfaces.

RapidIO 2.0 will ride on top of the 3.125Gbps Xaui electrical interface or the same OIF CEI PHY used by SPI-S. It will support one, two, four, eight or 16 channels. New features in version 2.0 include a streaming-packet format, virtual channels, a traffic-management specification and an endpoint flow control arbitration spec.

SPI-S will primarily be used to link framer and packet-processing chips. By contrast, RapidIO will be used for a broader variety of chip-to-chip, backplane and fabric applications, especially those requiring DMA semantics.

Signal-integrity issues
All the new interconnects are likely to raise new SI issues for board designers. "At 3Gbps across 30inches or so, you still have a reasonable eye at the transceiver," said Todd Westerhoff, VP for software at SiSoft. "But when you get to 6Gbits, there is nothing to measurethe game changes."

At 6Gbits and higher, transceivers routinely use signal-conditioning and filtering techniques to help capture signals across a board. But each chipmaker has its own approach to applying such pre-emphasis and equalization techniques. Engineers need a standard way to create a closed loop between the high-speed transmitters and receivers from various vendors so the chips work out their differences, Westerhoff said.

"All the 6Gbit systems will need some facility to let these two chips talk over control software to get optimized," he said. SiSoft is one of several companies working on products to address the issue.

Ramesh Sivakolundu, director of ASIC engineering at Cisco, said the company has faced many challenges with designs at 6Gbps and faster. These have included conforming to CRC24 and CRC32 specs, designing a good scrambler and descrambler scheme, and synchronizing the receiver and transmitter.

For many engineers, 6Gbit issues are still on the horizon. Most observers say the vast majority of high-speed interconnect design today is still being done at 1Gbps to 3Gbps. "A few companies have 5Gbit to 6Gbit stuff in the labs, but it's a small sample," said Westerhoff.

- Rick Merritt
EE Times




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