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Logic chipmakers seek 32nm breakthroughs

Posted: 01 Feb 2007 ?? ?Print Version ?Bookmark and Share

Keywords:32nm? lithography? high-k? ultralow-k? IBM?

Even as they put the finishing touches on their 45nm process technologies and tweak them for low power, leading-edge logic chipmakers are scrambling to find manufacturing breakthroughs for the 32nm node and beyond. At IEDM in San Francisco in December, vendors were grappling with a growing list of solutions, such as lithography tools, high-k gate dielectric materials and porous ultralow-k films.

Some experts even warned that there could be delays at 32nm due to the costs and complexities of the technology. The 32nm node for logic is slated for introduction in 2009 but could slip to 2010, said Ghavam Shahidi, an IBM Corp. fellow and director of silicon technology at the T.J. Watson Research Center.

"There is a chance it will move out," he said during a panel discussion at IEDM. "I would not rule that out."

On the other hand, chipmakers like Intel Corp. are determined to stay on the two-year process-technology path. "We're in the development phase for 32nm, which should be ready for 2009," said senior fellow Mark Bohr, the director of process architecture and integration at Intel. "But clearly, the challenges are becoming greater."

Power is driver
Design costs are expected to soar and could spiral out of control at that node, observers said. Chips will become more complex. And power consumption is perhaps the biggest concern. "Power is driving the technology," said Vivek Subramanian, an associate professor of electrical engineering and computer science at the University of California, Berkeley.

If that isn't enough, chipmakers face a plethora of manufacturing challenges, namely in lithography. Many leading-edge semiconductor makers are just beginning to insert their initial 193nm immersion lithography tools for production at the 45nm node. Intel, however, will continue to use conventional "dry" 193nm scanners at 45nm.

The cost for immersion lithography is already approaching $50 million per tool. At 32nm, many experts believe that chipmakers will extend their 193nm immersion scanners and deploy expensive double-patterning or double-exposure techniques.

Farhad Moghadam, senior VP and general manager of foundation engineering at equipment maker Applied Materials Inc., believes the 32nm node will mark a fundamental change in the industry. The critical IC-production technology today is lithography, but at 32nm and beyond, semiconductor manufacturing will shift to the "materials era," he said.

Chipmakers are moving toward high-k dielectrics for gate stack applications at the 32nm node. High-k could be introduced at 45nm, but the technology still faces some integration hurdles. "Vendors will need to have high-k by 32nm," said David Lammers, an analyst with VLSI Research Inc.

Besides high-k, Applied's Moghadam cited a slew of other materials changes, including porous ultralow-k films and strained silicon carbide, among others. New chemistries for chemical-mechanical polishing, etch, physical-vapor deposition and other processes will also be required at 32nm, he said.

While logic makers are worried about 32nm manufacturing, they are also scrambling to prepare for the 45nm node, slated for 2007. At IEDM, several vendors gave progress reports. The Crolles2 AllianceFreescale, NXP and STMicroelectronicspresented a paper on a low-power platform at 45nm. The platform makes use of immersion lithography, low-k films and a mask-free strain.

45nm bulk-CMOS
In another effort, Toshiba Corp., Sony Corp. and NEC Electronics Corp. said they have jointly developed a 45nm bulk-CMOS process technology. Using it, the team fabricated an embedded SRAM prototype with transistor performance more than 30 percent better than the previous generation.

The process includes immersion lithography, strained silicon and porous low-k insulator films. The team is using Nikon Corp.'s immersion lithography system, which has a numerical aperture of 1.07.

"We've integrated all technologies required for the 45nm CMOS logic," said Masaaki Iwai, chief specialist of the advanced logic technology department at Toshiba Semiconductor Co. The team expects that the process will be ready for mass production by the end of 2007.

Also at IEDM, the team of AMD, IBM, Sony and Toshiba said they had demonstrated a 45nm process. CMP can be performed without damaging the low-k film, which has a k-value of 2.4, said the companies.

For its part, Renesas Technology Corp. announced the development of a 45nm process for microprocessor and SoC products. The so-called CMIS transistor technology is a hybrid structure using metal gates for p-type transistors and conventional polysilicon gates for n-type transistors. It can be implemented without making major changes to current fabrication processes, thereby lowering production costs, according to Renesas.

The CMIS technology makes use of high-k materials for the p-type transistor formation. The high-k, which is made of hafnium silicon oxynitride, can be formed by adding fluorine ion implantation and minimal processing of a titanium nitride layer to the earlier fabrication process.

- Mark LaPedus and Yoshiko Hara
EE Times

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