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Circuit designer takes control over LOD parameters

Posted: 01 Feb 2007 ?? ?Print Version ?Bookmark and Share

Keywords:length of diffusion effects? circuit simulation? PDK functionality? LOD effects? Larry Aschliman?

Length-of-diffusion (LOD) effects in MOS BSIM models can impact analog circuit simulations at 130nm and below. These effects, also known as stress effects from the shallow trench isolation defining the transistor, are captured in the simulation by the instance parameters sa, sb and sd, the distances from the gates to the edge of diffusion. These distances affect device threshold and mobility, which affect matching of transistors, and can cause large errors in current mirrors.

The circuit designer would like circuit simulation to match post-layout simulation as closely as possible to avoid changes necessitated by differences in device operation between the schematic and layout. To help schematic simulation closely match post-layout simulation, the designer must predict how schematic devices will be combined in the layout and gain control over the parameters used to model the layout characteristics.

Predicting the layout depends on the link between the circuit and layout designers, and can be handled manually or automatically. Manual communication consists of notes on the schematic, while automatic communication is handled with tools like constraint editors. The ability to control simulation parameters depends on the process design kit (PDK) setup.

In Cadence's AMS design center, PDK parameters give the circuit designer control over LOD parameters. The first, a Boolean instance parameter, sets a more-relaxed value for sa and sb. Values are then set to a larger, fixed value (such as 3u).

After schematic simulation, the relaxed values are checked in LVS to be sure they've been satisfied in the layout. Actual values are extracted by physical verification tools and included in post-layout simulation. The Boolean parameter would be set if the designer expects the device to be placed in a transistor chain where the LOD effects would be minimized. For more control over LOD effects in sensitive circuits, we added the ability to edit sa and sb directly.

The choice of the number of dummy gates (tied in the "off" state) at the two ends of the transistor is also included in the MOS pcell for poly lithography control. It's also a way to increase sa and sb without adding source/drain capacitance to the substrate. The dummy parameter directly adds fingers to the transistor pcell layout, rather than expecting the layout engineer to add them by hand later.

Predicting LOD effects takes communication between circuit and layout designers. Best practices can mitigate LOD effects, and PDK can equip the circuit designer to successfully match post-layout simulation in the schematic simulation.

- Larry Aschliman
Staff Design Engineer, Cadence Design Systems Inc.




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