Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Engineers stress thermal impact on designs

Posted: 02 Feb 2007 ?? ?Print Version ?Bookmark and Share

Keywords:chip? EDA tool? chip design? DesignCon? Nicolas Mokhoff?

With increasing chip speed and density, designers are struggling to keep their cool while facing thermal challenges in all designschips, boards, modules and systems.

A DesignCon panel of engineers from chip, board, EDA tool and system companies shed light on the challenges and offered some solutions.

In selecting packages, chip designers should remember that comparing spec sheets can be misleading. "The commonly used thermal specifications of ThetaJCx and ThetaJMA can only be used for comparisons among packages, not how thermal features conduct in the system," said Javier DeLaCruz, packaging engineering and simulation manager at eSilicon. "No assumptions are made [about] how the package is used on a board. What's more, blocked air flow is not considered for chips and boards used in real applications," he said.

Thermal, power and electrical needs have to be addressed simultaneously. "There is need for tightly coupled codesigns of package and board, where the model of boundary conditions of package need to be applied to the chip," said Dian Yang, vice president of product management and general manager at Apache Design Solutions.

Yang said thermal impact in SoC designs is especially critical. "Leakage power increases with temperature, while dynamic power stays stable at 45nm," he said. "Clock skew is sensitive to temperature variation and the lifetime temperature characteristics of SoC-type ships can be as much as four times worse than at 65nm, when evaluating long-time reliability."

Optimal's chief technology officer and board member An-Yu Kuo listed the elements that must be simulated for use in system-in-packages designs. "Detailed models of the following are paramount: die, bond wires, bumps, balls, vias and local metal contacts." He emphasized that "chip, package and system designers need to interface."

Prabhu Sathyamurthy, director of the ICE business division at Fluent Inc. was more adamant about systems designed for data centers. "It's become the law to reduce the thermal dissipation of data servers in corporations," Sathyamurthy said.

Government mandates require the U.S. Environmental Protection Agency (EPA) to issue guidelines for both the public and private sector. A December 2006 law is part of EPA's Energy Star program, which encourages the use of energy-efficient products. "This will affect the entire industry food chain from chips to systems," said Sathyamurthy.

- Nicolas Mokhoff
EE Times




Article Comments - Engineers stress thermal impact on d...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top