Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > T&M
?
?
T&M??

VERTIGO project to work on TLM, RTL standards

Posted: 08 Feb 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Commission of the European Communities? STMicroelectronics? verification? VERTIGO?

The Commission of the European Communities within the Information Society Technology (I ST) area has launched a project to bridge the gap between system-level modeling and verification performed at the transactional level and the traditional RTL signoff description. The Commission partnered with industry companies STMicroelectronics, Aerielogic, and TransEDA Systems, and with four Europe universities for the project.

Named Verification and Validation of Embedded System Design workbench (VERTIGO), the project will check the consistency of different transaction level models (TLM) and the RTL, regardless of the refinement process used. The case studies, taken from embedded systems developed by ST, will focus on mixed-level/mixed-language flows, involving both TLM and RTL.

"We hope to achieve several technology breakthroughs with VERTIGO," said Umberto Rossi, ST's head of functional verification support and leader of the VERTIGO project. "The most important of these is the development of expression coverage criteria common to TLM and RTL that are capable of driving system validation between different abstraction levels."

Moreover, the VERTIGO project will investigate several formal techniques that contribute to different stages of the design-flow modeling and verification, and those that are integrated with the simulation-based approach. An assertion-based verification method will also be developed for static and dynamic verification with emphasis on TLM and the related metrics to measure their coverage. Finally, the project team will prototype a SW/HW co-verification environment, capable of driving the development of SW routines for embedded platform test.

VERTIGO will take the roadmaps of Accelera as reference for the development of verification standards and OSCI for TLM standardization. The project, which began in June 2006, will run until November 2008.




Article Comments - VERTIGO project to work on TLM, RTL ...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top