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Sematech to advance planar solution devt for 22nm

Posted: 09 Feb 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Sematech? CMOS? CMOS planar scaling? FinFET? SiGe?

Pushing forward with the planar transistor scaling strategy under its CMOS Extension Program, Sematech front-end engineers will combine planar CMOS approaches with new channel materials to develop transistors for the 22nm half-pitch technology generation. Sematech will also continue to investigate FinFET devices as an alternative to this.

"It appears there is still enough life left in planar scaling for the nearer term especially with the incorporation of germanium (Ge) into silicon (Si) devices, but that 3D devices and associated design capabilities will be needed to realize FinFET technology in the near future," said Raj Jammy, director of Sematech's front-end processes (FEP) division.

Sematech recently held an expert workshop with speakers and panelists representing planar CMOS and FinFET design and offering viewpoints on the benefits and issues of their respective technologies. Assessments from the technologists confirmed the direction of FEP's CMOS Extension Program, which also aims to examine non-planar CMOS device structures, including double-gate FinFETs and associated process development to improve their feasibility.

Hsing-Huang Tseng, chief technologist of FEP and program manager, explained that engineers have employed 'various tricks' to induce strain at the channel to improve mobility. However, he added that this approach may not be effective at 22nm and beyond.

"New channel materials are the direction we want to go," Tseng said, adding that options include SiGe, Ge and other untested elements in columns III-V of the periodic table. Sematech is investigating several variations of this approach, such as using Si or SiGe for NMOS and Ge or SiGe for PMOS channels, or III-V materials on Si platform for NMOS in the near future. These materials will be applied as ultrathin epitaxial layers grown selectively on Si to minimize defectivity.

"The idea of using two different materials in the channels for CMOS is relatively new, but is gaining momentum," Tseng noted.

He added that there are still serious challenges for extending the life of planar CMOS. These include reducing the defects in Ge or SiGe layers, ensuring that the mobility advantages observed for bulk materials are not lost when epitaxial channels are grown on Si and control of Ge band-to-band tunneling, which increases overall leakage current.

Beyond 22nm, Sematech will also probe on the usability of FinFET, which can give better short-channel control while offering greater speed. However, with numerous unsolved manufacturing and design challenges in implementing these 3D transistors with 22nm device dimensions, the workshop panel concluded that realization of FinFETs will require a serious effort to develop the needed design tools.

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