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Serdes cuts number of interconnect leads

Posted: 13 Feb 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Serdes? serial links? connectors? Fairchild? receiver?

Fairchild's FIN324C Serdes ICs

Serial links offer potential advantages over parallel links in terms of cabling, connectors and layout complexity, but often require parallel-to-serial format conversion at the source and the complimentary operation at the receiver. Fairchild's FIN324C ultralow-power series of Serdes ICs operate with just 4mA of current at 5.44MHz, and are housed in a space-saving BGA (3.5-by-4.5mm, 0.4mm pitch) or MLP (6-by-6 mm) packages.

Targeted primarily at cellphones and similar products with dual displays (one external, one internal), the dual-port devices have an MCU interface as well as multiple SPI ports. They operate from 1.6V to 3V supplies. They support 12bit and 24bit operation, and reduce the 12 or 24 LVCMOS signals in most cellphones to high-speed, differential signals, cutting the number of interconnect leads by as much as 6:1. These Serdes devices are designed to generate minimal EMI of -110dBm, which the vendor claims is 30dB lower than traditional LVDS signals, critical in such close-proximity applications. Susceptibility to radiated signals is also lower by at least 35dBm, due to the current sense receiver and differential signaling topology. They also provide 15kV of ESD protection.

The unique design reduces power and footprint requirements by implementing an architecture which eliminates the need for an internal PLL and need for an external clock. Prices begin at $1.66 (1,000 pieces) for the MLP version.

- Bill Schweber
Planet Analog




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