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Renesas, Matsushita advance on-chip SRAM process at 45nm

Posted: 15 Feb 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Renesas Technology? Matsushita Electric Industrial?

Renesas Technology Corp. and Matsushita Electric Industrial Co. Ltd have developed a technique for stabilizing the operation of on-chip SRAM manufactured at 45nm bulk CMOS.

The chip design approach was implemented with 512Kbit SRAMs and enabled stable operation over a temperature range from -40C to 125C and over a wide operating voltage range margin with respect to process variations. The SRAM chip incorporated two memory cell designs, one with a cell area of 0.327?m? and another with a cell area of 0.245?m?the 'smallest' level today. The smaller memory cell was achieved using a reduced processing dimension margin.

Overcoming voltage hurdles
The semiconductor industry has been developing techniques to achieve stable SRAM operation at 45nm however there has always been the issue of threshold voltage (Vth) variation affecting the 45nm process. To address this, Renesas and Matsushita employed two elements on its solution for a 6-transistor type SRAM memory cell. The elements include a read-assist circuit that performs automatic adjustment linked to Vth variations and a write-assist circuit that uses hierarchically structured power supply wiring.

The read-assist circuit employs the resistance of passive elements in a compensation function with a layout resembling a memory cell. Since memory cell variations and resistance value fluctuations are linked, the effects of Vth variations are reduced. The compensation function adjusts voltage automatically with respect to temperature and process variations. Thus, memory cell stability has been secured in read operations over a range of operating conditions, even if the symmetry of memory cell electrical characteristics degrades as temperature and process variations increase.

Meanwhile, the write-assist circuit adds finer power supply lines (divided into eight) to the memory cell's column-unit power supply lines so the isolation for the write operation is only performed where it is necessary. Also, it implements hierarchically structured power supply wiring. This lowers power supply line capacitance in critical areas, allowing power supply line potential to drop to a low potential at high speed. Measurements on the experimental chip confirm that even under worst-case conditions with -40C, as minimum operating voltage, and at worst-case process conditions, the write-assist circuit improves SRAM write speed compared to an SRAM design in which it was not employed.

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