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ST adopts Synopsys compiler for ASIC design

Posted: 15 Feb 2007 ?? ?Print Version ?Bookmark and Share

Keywords:STMicroelectronics? Synopsys Inc.? compiler? design compiler?

STMicroelectronics has deployed Synopsys Inc.'s Design Compiler topographical technology in its 90nm and 65nm ASIC design flow to eliminate design iterations and streamline the overall design cycle for its internal design groups and external customers.

Design Compiler topographical technology uses the Galaxy Design Platform physical implementation technologies to derive accurate interconnect delay data that allows the design compiler solution to predict post-layout design results such as timing, testability and area during synthesis. Moreover, topographical technology employs clock tree synthesis technology to estimate post-layout power results of the design, resulting in a highly predictable RTL-to-GDSII path.

"Topographical technology offers much-needed predictability for a convergent RTL-to-GDSII path. Front-end designers no longer have to wait for layout results to uncover critical design issues; they can identify and fix them up front. In turn, back-end teams receive a better netlist for physical implementation which is more likely to meet the desired performance," says Philippe Magarshack, group VP, central CAD and design solutions, front-end technology manufacturing, at ST.

Comments Antun Domic, senior VP and general manager, Synopsys implementation group. "We look forward to extending our collaboration with ST to support their ASIC customers through the broad deployment of topographical technology."

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