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Integrate 'hard' IP into an SoC

Posted: 16 Feb 2007 ?? ?Print Version ?Bookmark and Share

Keywords:IP integration into SoC? IP integration? intellectual property integration? IP block integration? Craig Zajac?

The integration of "hard" IP blocks lets system designers focus on their core competency by outsourcing certain blocks that previously had to be developed internally. Consequently, purchasing and integrating hard IP blocks is becoming a way of life for SoC designers. Off-the-shelf IP blocks are available for almost every functionfrom ADCs to Zigbee transceivers.

Selecting a quality IP supplier is a top concern in yielding a successful IP integration. To that end, the Virtual Socket Interface Alliance (VSIA) and the Fabless Semiconductor Association are working with companies to develop a standard, objective quality metric for hard IP blocks and their suppliers.

During the course of delivering such IP over the past several years, Impinj has witnessed a range of IP integration experiencesfrom the painless to the nearly disastrous. Most of the pitfalls can be avoided by following a few recommendations.


  • Read all the documentation. Impinj estimates that about 75 percent of the issues that arise during integration are a result of not thoroughly reading all the documentation, which includes datasheets and release notes. Most IP suppliers do a good job of delivering clear and concise documentationdesigners and project managers will be well-served by reading it.

  • Completely verify the process details. Unlike soft IP, hard IP blocks are normally developed and qualified for a specific process node, including foundry, geometry, flavor and I/O options. At advanced nodes, those details become more important.

  • Understand the maturity of the IP block you are integrating. Make sure that the project's risk tolerance is aligned to the overall risk of the IP block. The VSIA is developing a hard-IP quality metric that will provide an objective view of the overall strengths and weaknesses of an IP block's quality.

  • Use the simulation tools provided by the IP supplier. Most IP providers supply Verilog models and testbenches along with, or even prior to, the delivery of the final hard-IP block. Using those tools during the initial design phase should enable validation of 100 percent of the functionality and timing requirements, increasing the likelihood of success at final tape-out.

  • Plan for test access. All IP blocks need to be tested. Thus, understanding the specific test requirements of each block is critical. Design in such a way that you can deliver data to the IP block and view the signals returning from it. The blocks can sometimes be integrated into a standard scan chain; other scenarios may require special test modes.


  • Assume there are no layout restrictions with the IP block. Many hard IP blocks have keep-out areas where no high-speed or high-noise signals should be routed. It is also possible that the IP block will require a specific orientation to the wafer flat and will degrade if rotated in the layout. It is much easier to plan around the layout restrictions of the IP block if they are known ahead of time.

  • Assume the physical integration methodologies for the block are identical to the rest of the SoC. First, the GDSII layer mapping needs to match. For high-performance analog blocks, for example, it is common for IP suppliers to use a custom design-rule-check (DRC) or layout versus schematic (LVS) deck to verify their designs. Those decks are normally compatible with the standard foundry decks but will generate a known list of errors and exceptions. The IP supplier should include any expected violations in the overall design kit documentation.

  • Ignore the metal coverage around the IP block. Two conditions must be confirmed: the IP block itself meets all the required metal coverage rules, and the overall SoC has incorporated enough fill metal around the IP block to guarantee that the total design will meet the coverage rules in all regions.

  • Assume that ESD and latch-up pads are included. With Impinj's IP blocks, we count on the integrator to supply proven ESD and latch-up protection for all pads, with the exception of high-voltage supplies.

  • Neglect voltage requirements. The IP block will have voltage requirements specified at the input to the block. Voltage droop between the SoC power pin and the internal IP connection can cause the voltage at the IP to be out of spec, even when the main supply voltage is within spec. Also, check the power-sequencing requirements: Ideally, the power sequence required by the IP block should be investigated at the outset to confirm that it meets the overall application needs.

- Craig Zajac
Product Line Manager

- Troy Gilliland
Senior Engineering Manager

Impinj Inc.

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