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AMD bares first details of 45nm plan

Posted: 16 Feb 2007 ?? ?Print Version ?Bookmark and Share

Keywords:45nm? 65nm? microprocessor? processor? lithography?

Playing catch-up with Intel Corp., Advanced Micro Devices Inc. (AMD) has tipped the first technical details of its 45nm process technology.

The 10-metal-level process will use copper interconnects, porous low-k-dielectric films, embedded strained silicon and advanced annealing. It is unlikely that AMD will use metal gates and high-k dielectrics at 45nm, but it will deploy immersion lithography at that node for the first time.

AMD is collaborating on the 45nm technology with longtime partner IBM Corp. In 2005, the companies announced they would extend their joint process development work until 2011, covering the 32nm and 22nm process generations.

AMD claims to be closing the process gap with Intel. In December, AMD rolled out its first 65nm microprocessors and announced plans to introduce 45nm chips in mid-2008. "That will put us ahead of just about everyone," said Nick Kepler, VP of logic technology development at AMD.

Just about everyone, that is, except Intel. That company's first 45nm chipsthe Penryn family of processorsare due out in 2H, several months ahead of AMD's first devices.

Intel disclosed details of its 45nm process, which incorporates copper interconnects, low-k and strained silicon, a year ago. Unlike AMD, Intel plans to make 45nm devices by using conventional, 193nm "dry" lithography scanners instead of immersion tools. Intel mainly uses scanners from Nikon Corp. and chemical-vapor deposition (CVD) equipment from ASM International NV for low-k films.

For the critical layers at its 90nm and 65nm nodes, AMD has used dry 193nm lithography scanners from its main tool vendor, ASML Holding NV. But at 45nm, AMD will take the plunge into immersion scanners. The company will use ASML's TwinScan XT:1700Fi, a 193nm immersion tool with a numerical aperture of 1.2. That scanner will boost the depth of focus and provide a 40 percent gain in resolution, Kepler said.

The shift to immersion is a big and risky step for AMD. "These are brand-new tools," Kepler acknowledged. "But we have shown that the defect density for immersion is no higher than it is for dry tools."

For low-k, AMD used Applied Materials Inc.'s Black Diamond CVD-based technology up until the 90nm node. At 65nm, it switched to an IBM low-k film, dubbed SiCOH, which has a k-value of 2.7.

At 45nm, AMD will use an IBM film that will have porous features and a k-value of 2.4. "Our films parallel the offerings from Applied Materials in k-value, but with better mechanical properties," said John Pellerin, director of logic technology development at AMD, adding that the films "do run on Applied's tooling."

Another key for AMD is to scale its embedded SiGe technology to the 45nm node. The strained SiGe technology is key in an effort to boost mobility, and reduce power consumption and leakage in next-generation designs.

At the International Electron Devices Meeting, IBM and partners presented a paper on an embedded SiGe technology that uses IBM's graded germanium process. The retention of channel strain reportedly enabled a PFET performance gain of 15 percent over a non-graded solution.

- Mark LaPedus
EE Times




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