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IBM's eDRAM challenges Intel on cache

Posted: 22 Feb 2007 ?? ?Print Version ?Bookmark and Share

Keywords:eDRAM? SRAM? cache? memory? processor?

After a decade of research on embedded DRAM, IBM Corp. disclosed last week it will be able to pack as much as 48Mbytes of eDRAM on a processor or ASIC when its 45nm process technology comes online in 2008. The milestone could mark a shift toward using DRAM for cache in some chips.

In a paper at the International Solid-State Circuits Conference (ISCC), IBM described a 65nm prototype embedded DRAM with a latency of just 1.5ns and a cycle time of 2ns. That's an order of magnitude faster than today's DRAMs and is competitive with SRAM, which is typically used for microprocessor cache memory.

"To put 24Mbytes to 36Mbytes of memory on a chip, you would need a 600mm? die today. Using this technology, you could put that much memory on a 300- to 350mm? die," said Subramanian Iyer, a distinguished engineer and director of 45nm technology development at IBM.

The company expects to use the technique on its future Power and Cell processors as well as have it available for its ASIC customers. "It's being defined in a way that it can be part of our standard 45nm process technology," Iyer said.

IBM's upcoming Power6 CPUs use 8Mbytes of SRAM cache. Rival Intel Corp.'s Itanium chips use as much as 24Mbytes.

By tripling the cache on a CPU, IBM could double the chip's performance, Iyer said. But an analyst challenged that claim.

"I have my doubts about that," said David Lammers, director of the WeSRCH Web site for market watcher VLSI Research Inc. "Typically, if you quadruple the amount of cache, you cut the amount of cache misses by a factor of two, but that doesn't necessarily double the chip's performance."

Lammers nonetheless said the eDRAM capability could give IBM and process development partner Advanced Micro Devices Inc. (AMD) an edge over archrival Intel. But Intel said it will be able to deliver as much cache as IBM at 45 nm using its SRAM designs.

Meanwhile, Lammers said he believes Intel is ahead of IBM in delivering high-k materials for 45nm technology, which will give its chips an edge in performance and power. IBM and AMD may not have high-k materials available until a second generation of their 45nm process or until they hit the 32nm node, he said.

"In a way, it's apples and oranges," Lammers said. "IBM will score in servers by integrating eDRAM," but Intel will have a performance and power advantage with high-k that could help all its processors.

For its part, Intel is sticking with SRAM cache for the foreseeable future.

"We think we have not only the smallest SRAM cell, but a design with great performance and yield," Mark Bohr, director of process architecture and integration at Intel, said in an interview on the ISSCC floor. "With eDRAM, you don't get the best cell size, and you can degrade logic performanceand it's expensive."

Bohr, who co-authored an ISSCC paper on a low-power SRAM for mobile systems, noted that Intel is already packing 24Mbytes of SRAM cache on its dual-core Itanium, made in a 90nm process. "We have the capability to put more memory on chip at 45nm," he said.

Nevertheless, IBM's advance may be the start of a trend. Lammers noted SRAMs have an increasing number of problems, including the relatively large size of their typically six-transistor cells.

"SRAM is hanging in there, but it's struggling with soft error rates and read disturb problems. We may see a transition to eDRAM for some applications," Lammers said.

Because of random doping fluctuations, IBM's Iyer said, "SRAMs are not scaling well."

Memory accounts for as much as three-quarters of the area of today's MPUsa figure that could rise to 90 percent by 2010, Iyer added.

"Processors are definitely cache-starved, and as you go more toward multicore processors, the need for memory integration becomes more acute," said Iyer. "There are some server chips that could not be made without this technology."

- Rick Merritt
EE Times

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