Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

IAR Systems upgrades visualSTATE design tool

Posted: 26 Feb 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Embedded Workbench? YellowSuite? IAR Systems? visualSTATE? verification tool?

IAR Systems has launched the latest version of its state machine embedded design and verification toolvisualSTATE 5.4featuring a tighter integration to IAR Embedded Workbench. The new features of this upgraded version allow both project expenditure and implementation time to be reduced. It promises a truly integrated and iterative workflow, from design through verification to validation and debugging on hardware.

Formalized approach
visualSTATE offers a simple formalized approach to the design phase, based on the state machine subset of UML, which is much easier to learn than full UML. It can handle thousands of concurrent and hierarchical state machines in one design, and provides formal verification and validation functions that ensure a higher quality product reaches the market. visualSTATE automatically generates compact C/C++ source code that is 100 percent consistent with the design.

The integration with the IAR Embedded Workbench IDE is realized as a C-SPY plug-in that displays visualSTATE design model information in the C-SPY debugging environment within IAR Embedded Workbench. The tool suite provides either full simulation or hardware debugging of the design with meaningful, high-level visual feedback into the state machine model rather than the C-level feedback that would be provided with alternative methods. For example, this allows the user to easily set complex breakpoints on the design level, instead of using complicated and error prone C level data breakpoints.

Increased efficiency
Version 5.4 of visualSTATE gives users the benefit of increasing test phase efficiency, because the initial code quality is improved by applying formal verification and early function validation. Using formal methods of verification, it is possible to find a number of errors and mistakes that would be virtually impossible to find by conventional means. The formal verification tests include the detection of unreachable states; dead end states; 'live lock' states; ambiguous assignments and transitions; and unused events, transitions, variables, states and action functions.

The graphical design approach of visualSTATE means that intra-team communication is improved, as is the production of meaningful and consistent documentation. Maintenance costs are also lowered because of the simplicity of the design approach and the ease of navigation as well as the ability to change core application logic in a very simple manner.

Complete tool suite
The new version of visualSTATE forms a key component of IAR YellowSuite, the completely integrated tool suite for development of embedded systems.

The integration between visualSTATE and IAR Embedded Workbench is available for the vast majority of 8-, 16- and 32bit architectures supported by IAR Systems.




Article Comments - IAR Systems upgrades visualSTATE des...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top