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Minimize FPGA power consumption

Posted: 26 Feb 2007 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? ASIC? CPLD? power management? programmable logic?

By Hezi SaarM
Actel Corp.

With stricter system power limits, specs and standards that cap the total power consumed, system designers are increasingly challenged.

Traditionally, ASICs and CPLDs have been clear winners in the low power game. But CPLDs used in some low-power applications are losing their effectiveness, mainly due to relative high costs and the increased demand for high-end features and extra logic. ASICs are also becoming riskier.

Increasingly, programmable semiconductor devices, such as FPGAs, are becoming the preferred solution.

When creating a new design, consider BOM, cost, power, board size and time-to-market. After prioritizing the initial requirements, the designer should consider several factors before selecting an FPGA to implement the design.


  • Profile your design. How long will the FPGA run at high speed, vs. low speed or with stopped clocks? Can burst-mode processing at a higher clock frequency, but with more device sleep time, achieve the required throughput? Is it better to run the design at a lower clock frequency for longer periods of time? FPGA suppliers provide power analysis and prediction tools to help in this process, but some tools are overly optimistic.

  • Calculate power consumption for each product state.

  • Account for power consumed in all states over the product lifetime or expected battery operation time. Consider power-up, standby, idle, dynamic and power-down states. An FPGA in a consumer handheld device with Wi-Fi communication might have a power profile of 5 percent active, 20 percent static and 75 percent sleep.

  • Calculate the worst-case static power consumption. Newer FPGA technologies may have higher static power consumption than designers might realize, particularly over extended temperature ranges. Make sure to consider core, I/O and any auxiliary power supplies. When calculating static power consumption, P = IV for each component.

  • Analyze the temperature and voltage changes expected over the product power profile. Heat and voltage changes over the product operation time need to be accounted for.

  • Determine battery operation time for each system alternative (for example, high performance for short periods, lower performance for longer periods) to determine the most appropriate one.


  • Forget to use low-power modes. Some power-saving modes require board considerations for implementation, so the design should be able to accommodate that. Some modes cannot be used, because of complex implementation or prohibitively long amounts of time required for the application to enter or exit the mode. For example, low-power modes offered by SRAM or SRAM hybrid FPGAs require device reconfiguration with an associated power surge up to 1W.

  • Let user static RAM and high I/O voltages sink excessive power. When creating clock regions using local or regional clock resources, use "enabled" logic to disable clock transitions in the system. User static RAM can sink excessive power; therefore, look for techniques to minimize RAM usage. I/Os can also sink a great deal of board power. Use low-voltage TTL standards and lower I/O voltages. Serial low-voltage differential signaling chip-to-chip data transfers using double-data-rate registers may save power over parallel off-chip buses. Check whether components can be integrated or functionality minimized. A bigger FPGA may accommodate a soft microcontroller and save power.

  • Rely solely on measured power data. Base your calculations on data sheet and power estimator numbers, and ask how those numbers were obtained. Do the numbers also take silicon variations into account? Remember, what is measured on the bench today may vary significantly from what may ship as a low-power device tomorrow. Be careful when basing power calculations solely on measured data.

  • Omit power consumption levels of additional components. Sometimes, implementing solutions with a certain FPGA technology may require additional components. For example, memory may be required for bootup, whereas nonvolatile FPGAs offer single-chip implementation.

About the author
Hezi Saar
is product-marketing manager at Actel Corp.

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