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EDA 'troublemakers' debate at DVCon

Posted: 27 Feb 2007 ?? ?Print Version ?Bookmark and Share

Keywords:CPF? IC design? IC design verification? design verification? low power standard?

The annual "EDA Bigwigs" panel at the Design and Verification Conference (DVCon) was renamed the "Troublemaker's Panel" this year for good reason. Confronted with provocative questions, EDA vendor representatives debated such topics as low-power standards, Cadence Design Systems' Skill language, and outsourcing to India.

As in previous years, the DVCon panel was moderated by John Cooley, whose Deepchip web site listed "edgy questions" sent in by EDA users prior to the panel. Companies represented in the Feb. 22 panel included Cadence, Mentor Graphics, Synopsys, Magma Design Automation, Sequence Design, Clear Shape Technologies and Forte Design, in addition to EDA analyst Gary Smith.

The most contentious debate arose when Cooley asked why the EDA industry can't have one low power standard. Ted Vucurevich, Cadence CTO, started talking about Cadence's Common Power Format (CPF) as a "standard based on something that actually worked." He didn't get far before being interrupted by Rajeev Madhavan, Magma CEO.

Magma has a low-power implementation that works too, Madhavan said, and Magma, Mentor, and Synopsys all worked together and contributed to Accellera's Unified Power Format (UPF). "We would welcome Cadence to that effort," Madhavan said, "but not to say, 'this is my format and you can't change it, and we have veto power.'"

Vucurevich insisted CPF is "open," resulting in instant "no it's not" retorts from Madhavan and John Chilton, vice president and general manager of Synopsys' solutions group. "We're legally prevented from looking at CPF, so I don't think it's very open." Chilton said Synopsys was initially asked to sign an NDA and promise not to work on a competing format in order to view CPF.

The Cadence CTO replied that anyone can join the Silicon Integration Initiative's (Si2) Low Power Coalition and not only review CPF, but contribute to it. "Anyone in this room can get UPF," Chilton responded. "Maybe six people in this room can get CPF."

Going through an Accellera process with CPF, Vucurevich suggested, could take a couple of years. Vucurevich was then informed that Accellera had approved a UPF 1.0 specification that very day. "Well, good for Accellera," he responded.

Chilton noted, however, that once Si2 makes the CPF specification availableexpected during the next couple of weeksit should be possible to converge CPF and UPF into one standard. "We won't be able to sustain two efforts," he said. "The industry will force them together."

Vucurevich also found himself on the defensive regarding Cadence's proprietary Skill language, used to build parameterized cells (p-cells) for analog and custom design. Cadence has been under pressure to open Skill so p-cells can be portable to any application that runs on OpenAccess.

Chilton commented that the OpenAccess database is reasonably open, but not very useful. "It would be much more interesting if Skill and p-cells were open," he said. "That's the last closed citadel in the EDA world for interoperability."

"Bluntly, that's not going to happen," Vucurevich replied. "We're not going to open from a competitive point of view and say here's a free ride for coming in and trying to take over accounts."

Vucurevich said that Cadence's approach to interoperability has "enabled" other providers to step in, such as Ciranova Inc., which last year rolled out a solution that lets users migrate legacy Skill p-cells to any application based on the OpenAccess database. "We're neither happy nor displeased," Vucurevich said. "It's not a problem at all." Later, Vucurevich confided that Cadence is working on a solution that will allow p-cell migration.

Despite controversies, the panel ended on an up note as both Madhavan and Chilton said the EDA industry is experiencing good growth and is no longer flat. "There's a revolution out there," Chilton said. "We're still giving tremendous value to our customers."

- Richard Goering
EE Times

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