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PCIe, GbE, XAUI protocol packs roll for Xilinx Virtex-5 FPGAs

Posted: 28 Feb 2007 ?? ?Print Version ?Bookmark and Share

Keywords:PCIe? GbE? XAUI? Xilinx? Virtex-5?

Xilinx Inc. has announced the availability of protocol packs for PCIe, GbE and XAUI for its 65nm Virtex-5 family of FPGAs. The company also released protocol-specific characterizations reports for SONET OC-48/SDH STM-16 and Common Public Radio Interface (CPRI). Each standard protocol pack includes protocol specific PHY characterization reports, interoperability and compliance reports, IP cores and documentation to facilitate low-risk and efficient implementation of standardized high-speed serial protocols in Virtex-5 FPGAs.

Virtex-5 LXT samples have been available since May 2006 and all Virtex-5 available devices are currently characterized across process corners, voltage and temperature (PVT) for key transceiver performance specifications (such as transmit jitter generation and jitter tolerance), compliance test suites and rigorous test programs and with third-party devices to ensure predictable performance in user applications. The RocketIO GTP transceivers in Virtex-5 devices support a multitude of protocols. With protocol specific characterization of this kind, users can reduce design cycle time by orders of magnitudes. To achieve this milestone, Xilinx has employed a layered characterization methodology testing the common aspects of multiple protocols first and then testing protocol-specific requirements.

In addition to protocol characterization, each protocol pack provides interoperability certification data of the solution (device, hard and soft IP including PHY and link layers) ensuring compliance with a standard's specifications. Xilinx actively participates at standards body certification events to ensure compliance.




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