Clocking High-Speed A/D Converters

Extremely high-speed ADCs demand a low-jitter sample clock in order to preserve SNR. These 8bit and 10bit converters have best-case noise floors set by quantization noise. In this article, we look at the strategy for optimizing the performance of the sample clock based on PLL/VCO characteristics. This means minimizing overall integrated phase noise, which minimizes clock jitter.

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