Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Amplifiers/Converters
?
?
Amplifiers/Converters??

Clocking High-Speed A/D Converters

Posted: 27 Feb 2007 ?? ?Print Version ?Bookmark and Share

Keywords:ADC? clock? PLL? CO? converter?

Extremely high-speed ADCs demand a low-jitter sample clock in order to preserve SNR. These 8bit and 10bit converters have best-case noise floors set by quantization noise. In this article, we look at the strategy for optimizing the performance of the sample clock based on PLL/VCO characteristics. This means minimizing overall integrated phase noise, which minimizes clock jitter.

View the PDF document for more information.




Article Comments - Clocking High-Speed A/D Converters
Comments:??
*? You can enter [0] more charecters.
*Verify code:
Related Datasheets
Part Number Description Category
? ADC08D1500 High Performance, Low Power, Dual 8-Bit, 1.5 GSPS A/D Converter from the PowerWise? Family Cards and Modules

?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top