Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > FPGAs/PLDs

Boost ECC, solve NAND flash issues

Posted: 01 Mar 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Toshiba? NAND flash? error correction code? ECC? Samsung Electronics?

Toshiba Corp. is rolling out four enabling technologies in a multipronged drive into the booming embedded NAND flash-memory market.

The technologiesaimed at boosting the error correction code (ECC) functions and addressing other design problems with NAND flashinclude logical block addressing (LBA) NAND; gigabyte NAND; Gbyte multichip package (MCP); and package-on-package (PoP). LBA-NAND and Gbyte NAND are single-component solutions while Gbyte MCP and PoP are chip packages.

The solutions use Toshiba's new 56nm, multilevel cell (MLC) NAND flash devices. Toshiba expects the market for embedded NAND to grow from $6.3 billion in 2006 to $12.9 billion in 2010. Toshiba is the world's second-largest NAND flash supplier, after South Korea's Samsung Electronics Co. Ltd.

Designs incorporating NAND flash are exploding in consumer electronics. But NAND also poses inherent challenges for designers, such as a shift from 4-6bit ECC and complex software drivers.

Another headache is the transition from single-level cell (SLC) NAND architectures to MLC devices.

"MLC requires better error correction," said Doug Wong, a member of the technical staff at Toshiba's U.S. chip unit, Toshiba America Electronic Components Inc.

To help designers on that front, the company has rolled out 56nm devices based on two technologies: LBA-NAND and GB NAND. Today's NAND flash employs the physical-address access method that defines each physical page of a memory, from the chip to the block, to the page and down to the cell. Engineers must develop host-side and driver specifications that can recognize and accommodate this physical addressing or use third-party controllers.

LBA-NAND, Toshiba said, solves many of those issues. The logical-address access method of LBA assigns each cell a unique address that is not geometry-dependent. The first cell is simply 0, and numbering will continue to cover every cell. Assigning a new address to each cell allows increases in memory capacity to be accommodated more easily.

That approach also allows block management, ECC and wear-leveling-all of which are controlled by the host side and will be handled on the memory side by the LBA-NAND controller.

Single-package solution uses as many as four MLC NAND chips.

Toshiba's first LBA-NAND parts, built in a 56nm process, are available in 2-, 4- and 8Gbyte capacities. The products also boast 8bit ECC, 10,000 write/erase cycles, 5Mbps write performance and greater than 10Mbps read performance.

The 2Gbyte and 4Gbyte devices are slated for production in Q2; Toshiba did not disclose the schedule for the 8Gbyte product. The parts come in a 48-pin thin small outline package and are drop-in replacements for comparable SLC NAND devices.

- Mark LaPedus
EE Times

Article Comments - Boost ECC, solve NAND flash issues
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top