Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Asynchronous interconnects need innovative tools

Posted: 01 Mar 2007 ?? ?Print Version ?Bookmark and Share

Keywords:EDA tools? EDA vendor? self-timed circuits? asynchronous interconnect for complex chips? innovate or vacate?

Fritz: There is no fundamental reason that additional non-timing-based constraints cannot be added to existing tools.

Take a cursory look at the SoCs on the drawing board. You'll see some common problems stemming from design requirements that encompass dozens of intellectual-property cores, very high-speed clocks, multiple clock domains and the ever-present need for lower-power dissipation. These characteristics have fueled interest in self-timed, asynchronous interconnects for complex chips. Unfortunately, today's EDA tools are not equipped to handle the circuitry necessary to produce such chips.

Today's EDA tools lack the ability to describe the more complex constraints used by self-timed circuits. Instead, they remain slanted toward the simpler, synchronous circuits commonly used today. For example, try synthesizing asynchronous circuits with current logic-synthesis tools; you get wildly incorrect gate and buffer sizing because of the overly simplistic approach such tools take toward combinatorial loops. While such loops often occur in complex combinatorial logic in synchronous designs, they are handled in a naive way that may be fine for most flop-to-flop signaling. But what if there are no flops?

Current static timing-analysis tools also have problems for similar reasons and often default rather than handle the nested looping circuits of self-timed design.

What's needed is for large EDA vendors to help enable this new self-timed technology, rather than simply ignore it because it lies outside their comfort zone. We pay exorbitant amounts for EDA tooling annually, and yet there has been little advance in these tools since before the turn of the century. There is no fundamental reason that additional non-timing-based constraints cannot be added to existing tools. For various reasons, however, leading EDA vendors have been reluctant to embrace this up-and-coming technology.

On the other hand, many of our most prestigious universities are paving the way for asynchronous technology to bolt into the mainstream. Every year, international gatherings at asynchronous conferences grow in depth and breadth. Yet EDA vendors continue to turn a blind eye.

This position is not surprisingindeed, it bears a striking resemblance to the transition from schematic capture to HDL synthesis that catapulted today's EDA giants into their dominant positions.

As Clayton M. Christensen pointed out in his popular book The Innovator's Dilemma, this very process of ignoring disruptive technologies will eventually bring down the giants of an industry.

The story is the same for everyoneinnovate or vacate. This can be done by evolution or revolution.

The question is: Which will it be?

- David Fritz
CEO, Silistix Ltd

Article Comments - Asynchronous interconnects need inno...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top