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NEC develops technology for design, quality inspection

Posted: 02 Mar 2007 ?? ?Print Version ?Bookmark and Share

Keywords:signal jitter? LSIs? internal operating margins? observe internal operating margins?

NEC Corp. and NEC Electronics said they were successful in developing a technology that introduces signal jitter into an LSI's internal clock to accurately observe the internal operating margins of an LSI. The technology has an on-chip clock jitter formation circuit. It also features new design and quality inspection schemes when combined with other measurement technologies. The technology is aimed to overcome performance and cost issues associated with the development of ultra-fine, large-scale LSIs.

The on-chip clock jitter formation circuit intentionally introduces jitter and periodically switches between clock signals with long and short oscillating frequencieswithout changing oscillating frequency of the clock signal introduced from outside the LSI. With this, jitter can be introduced into the clock signals without affecting the communication between devices or between circuit blocks within a given LSI. This enables a designer to observe operating margins with a high degree of accuracy during chip selection tests and during operation of a system in which an LSI is mounted.

When the technology is combined with physical quantity measurement circuits related to internal quality (such as power voltage fluctuations), engineers can identify the causes and locations of LSI instability and respond to these conditions anytime, improving validation of chip quality.




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