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Freescale reduces EDA tool flow

Posted: 05 Mar 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Freescale Semiconductor? IC design? IC verification? EDA? EDA tool?

Freescale Semiconductor has reported significant design efficiency improvements and a sizeable reduction in the number of EDA "tool flows" the company supports in its global development and design activities around the world.

The new design milestones were achieved, in part, through a collaborative multi-year agreement that designated Cadence Design Systems as Freescale's primary EDA vendor.

"It was not easy" Chekib Akrout, vice president, design technology for Freescale, noted of the design system overhaul, still ongoing, that has resulted in a "streamlined tool flow" that cut the number of supported tool flows "from more than 15 to 3 or 4" across "all tools, methodologies and design groups" in its primary analog, analog-mixed signal and digital lines.

The consolidation also involved all of its design centers in the United States, Israel, India and China and resulted "almost a 20 percent efficiency improvement" in resource and expenses supporting its design capabilities, including lines supporting its 65 nm and 45 nm process technologies.

Freescale spends about $1.3 billion annually on R&D, a significant, but unspecified percentage of which goes for EDA tool acquisition and support. Improvements on this scale would not only benefit the chip maker's asset utilization in the eyes of its new private equity owners, but also Cadence. According to Akrout, Freescale has improved its gross profit margins in the past year and a half from 38 percent to 46 percent, much of it based upon "improvements in manufacturing process discipline."

Cadence held its annual analysts meeting in New York where it invited Akout and Freescale to participate in a "customer panel," session. It's all part of a new campaign to amplify the EDA software supplier's new mantra, and support its strategic marketing objective of extending its EDA franchise from simply being a tool supplier to one of an "enterprise product development" company and purveyor of innovative technology solutions up and down the semiconductor design and development chain.

When announced, Freescale noted that the so-called preferred supplier agreement had the objective of "collaboratively developing technology," something that's apparently been achieved.

"We have been highly interactive with Cadences' R&D team" Akrout said noting close cooperation deep within the R&D organizations of both companies.

One of the chief hurdles Freescale faced in evaluating and optimizing its diverse, multi-branched tool flows were things like "what is the incremental value of any specific element or tool in the flow, and what does it contribute to design improvement?

"Is it two percent? Three percent, and how do we prove it? Does that mean the chip is three percent faster?"

Chekib made frequent references to this type of assessment as his team reworked tool sets up and down the design chain, a process that compelled Cadence and all other vendors in the chain to justify its overall, not just point, contribution to the project.

Freescale's design chain rework challenges an entrenched mentality in the world of EDA which has tended to result in tool chains comprised of multiple, sometimes not-interoperable, "best in class" design software tools. Chekib's team included his engineering teams and designers in the design flow transformation, forcing the company to make hard decisions about economic efficiencies, engineering costs and support costs for all of the tools in its 15 design chains. Through this process it was able to streamline and eliminate many redundant and inefficient processes, tools and steps in its progression down to "three or four" tool flows, Chekib stated.

According to James Miller, Jr. Cadences' executive vice president, products and technology organization, Freescale is not the only semiconductor maker looking at and working on this type of EDA transformation "but it's in the vanguard."

"We've achieved a lot but there always more we can do," Akrout conceded, noting that the EDA tool and process improvement project is ongoing, especially in areas such as design-for-manufacturing and other aspects of its internal manufacturing and customer support 'ecosystem.'

"It's not just about cranking the clock for performance improvements," he observed, noting that "we have a lot of fundamental work to do, especially in multicore," a reference to the adoption of new microcontroller architectures that require a revamping of Freescale's software development, compiling and debugging processes."

- Richard Wallace
EE Times Europe

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