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Cadence platform enables Taiwan's first 65nm chip design

Posted: 15 Mar 2007 ?? ?Print Version ?Bookmark and Share

Keywords:65nm process? design? verification? Cadence Design? Encounter GXL?

Cadence Design Systems Inc. announced that with the use of its Low-Power Solution and SoC Encounter GXL RTL-to-GDSII system, Global Unichip Corp. (GUC) was the first Taiwan-based design company to complete a successful tapeout of a 65nm device.

"Targeting a 65nm process technology is the state-of-the-art in semiconductor design," said Jim Lai, president and COO of GUC. "With comprehensive know-how of advanced technology designs, GUC used the combination of the Cadence Low-Power Solution and Encounter platform to build this low power design with over ten-million gates and implement it within seven weeks, which in turn helps GUC's customer to achieve a significant time-to-market advantage."

The GUC tapeout also involved a customer design that is slated to move into production. GUC designed the chip using the Cadence SoC Encounter system, Encounter Conformal technology, and CeltIC SI-aware nanometer delay calculator. The Taiwanese company achieved higher quality of results using the design-for-yield features and design-for-manufacturing capabilities of SoC Encounter GXL, including virtual CMP and critical area analysis tools.

Many of the tools used by GUC in this design are also part of the Cadence Logic Design Team Solution, which helps logic design teams improve schedule predictability through plan-to-closure management and logical signoffin an integrated and holistic approach covering both design and verification.

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