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Actel offers free IP cores for FPGAs

Posted: 16 Mar 2007 ?? ?Print Version ?Bookmark and Share

Keywords:IP controller core? FPGA? free intellectual property controller cores? free IP controller core? free IP core?

Expanding its offerings for embedded systems designers, Actel Corp. is rolling out a pair of free intellectual property (IP) controller cores that are optimized for its FPGA products. The two IP cores are the CoreABC, an RTL-programmable, soft micro core, and the Core8051s, an 8bit controller IP core based on 8051.

With the announcement, Actel is expanding its controller/processor IP portfolio from three to five products. Its earlier offerings include a standard 8051 core in the 8bit space and two 32bit devices, the ARM-based CoreMP7 product and the Leon3 processor. The Leon3 is a 32bit, Sparc-based processor developed by Gaisler Research AB.

The CoreABC and Core8051s represent Actel's entry-level IP offerings, said Mike Thompson, senior manager for IP product marketing. The 8bit controller market still has legs despite a shift toward 32bit products for embedded applications. "People are also still using the 8051 architecture. The demand is still growing for 8bit products," said Thompson, although "32bit shipments are growing the fastest."

The company offers all of its controller/processor IP for free with the intention of making its FPGA offerings attractive to designers. "We're in the business of selling silicon," Thompson said. "We're making it easier for customers to use our products." All cores can be used with Actel's single-chip FPGAs.

The new cores are geared for a broad range of embedded-control applications.

The CoreABC is a soft micro offering that features deterministic operation and an Advanced Peripheral Bus (APB) interface. With an I/O response time of less than 100ns, the core can be configured from 241 (8bit data width) to 1,030 (32bit data width) tiles, which are small and programmable.

Configurable soft micro features 241 tiles. CoreABC is RTL or software-programmable.

The core supports frequencies from 17-94MHz, and from 32 to 1,000 instructions. Implementation starts at less than 10 cents "per instantiation," according to Actel.

Compatible with the industry-standard 8051 ASM51 instruction set, the Core8051s is a configurable solution that consists of 2,642 tiles. It features one clock per instruction, which is 30 times faster than the original 8051, according to Actel.

The Core8051s connects to the APB bus for integration with other APB peripherals using Actel's CoreConsole tool.

- Mark LaPedus
EE Times




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