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Lattice offers 533Mbps DDR2 SDRAM controller IP

Posted: 16 Mar 2007 ?? ?Print Version ?Bookmark and Share

Keywords:DDR2? SDRAM? FPGA? Lattice? controller?

Lattice Semiconductor Corp. offers the highest possible data rate for a low-cost FPGA with the introduction of the industry's first 533Mbps DDR2 SDRAM controller IP core. The DDR2 SDRAM IP core is optimized for the company's low-cost LatticeECP2 and LatticeECP2M FPGA families, as well as its high-end LatticeSCExtreme Performance FPGA family.

The DDR2 SDRAM controller IP core interfaces seamlessly with industry-standard DDR2 SDRAM memory devices and has been performance-tuned for Lattice FPGAs. This IP core supports all DDR2 commands, and features intelligent bank management to minimize active commands, a synchronous implementation for reliable operation and a command pipeline to maximize throughput. The most common memory configurations are supported through a combination of variable address widths for different memory devices, programmable timing parameters, byte-level writing through data mask signals and burst termination.

High-performance I/O
A primary feature of the LatticeECP2 and LatticeECP2M architectures is their pre-engineered, high-performance parallel I/O that supports generic LVDS standards at speeds up to 840Mbps. By leveraging the FPGA fabric capabilities, the DDR2 SDRAM controller IP core is able to interface at a speed of 266MHz, resulting in a data rate of 533Mbps, said Lattice.

The DDR2 SDRAM controller is an IPexpress User Configurable IP core. The IPexpress design flow, included as a standard feature in Lattice's ispLEVER design tool suite, allows designers to configure the core, generate netlists and simulation files, and evaluate the core in hardware before purchase.

- Gina Roos

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