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Tap high-speed FPGA transceiver for PHY

Posted: 16 Mar 2007 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA transceiver? choosing high-speed FPGA transceivers? design criteria for FPGA transceiver? considerations for choosing high-speed FPGA transceiver? Stratix II GX FPGA?

Many standards and protocols now use high-speed transceivers (Serdes) for the physical interface. These cover a variety of applications including communications, computer, industrial and storage systems, which need to move large quantities of data between chips and chips/modules, or across backplanes or cables. Yesterday's parallel bus interfaces can no longer accommodate the speed and data-transfer requirements of today's applications.

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