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Electrical DFM promises gains in parametric yield

Posted: 16 Mar 2007 ?? ?Print Version ?Bookmark and Share

Keywords:DFM technology? DFM techniques? parametric yield loss? equivalent scaling? manufacturing technology?

As the IC industry moves into the 45nm node and beyond, manufacturing technology faces ever-greater challenges of pitch, mobility, variability, leakage and reliability. Design techniques are under greater pressure to provide "equivalent scaling" to enable the IC road map to continue in a cost-effective way.

Design technology provides equivalent scaling. Traditional, "classical" scaling refers to the shrinking of physical geometries with each successive process node, without any changes to the underlying materials used. A look at the history of the International Technology Roadmap for Semiconductors shows that this type of scaling hit a "red brick wall"?a wall of technology requirements with no known solutions?at 180nm.

When classical scaling fails, Moore's Law trajectories of performance, density and cost are continued through equivalent scaling, notably via new design technologies that reduce power or improve density without requiring any innovation in the process technology. By using equivalent scaling, design technology can "share" the burden of overcoming the red brick walls of the IC road map. Indeed, design technology promises to wring a huge amount of untapped value from current silicon process technologies.

What's left on the table today? Conservatively speaking, one-half of a process node of power, a third of a node of area and a full node's worth of performance are left. Without question, this is a sweet spot for returns on R&D and tool investments.

Process data isn't the solution. At 180nm and above, manufacturing requirements were fairly straightforward and embodied in width and spacing rules for each layer. As long as those rules were obeyed, the designer could rely on the chip's working as intended. With each new process generation, however, design rules have become more numerous, more complex and even subject to conflicts.

Designers face an unfortunate Moore's Law corollary today: an explosion of absolute, context-dependent and recommended rules that appear?usually without any explanation?in an ever-thicker design rules manual. Fabless IC companies have been vocal about the need for detailed process information that helps to analyze and compensate for process complexity and variability.

However, foundries have been reluctant to release this highly sensitive and confidential information due to competitive reasons. Moreover, such data can potentially change the nature of the foundry-fabless IC company contract. Imagine if a foundry had to sign up to the exact process statistics to which a design was optimized. Even worse, consider that bleeding-edge process models may be obsolete before the design is completed?and that design optimizations targeted to early models may actually be harmful in the matured process.

Separate concerns
Recently, foundries have started to give ground, making some process model data available in encrypted form.

But that poses a new dilemma: Now that chip designers have access to process information, what do they do with it? How should statistics of Vt variation due to random dopant fluctuation or a CMP model affect the way the chip designer performs synthesis, place and route?

Practically speaking, it shouldn't. Designers have enough to worry about without having to become process experts as well.

We cannot expect chip designers and process engineers to become cross-disciplinary experts overnight?and it's not clear that this is even desirable. The separation of concerns that exists between design and manufacturing is a fact of life even among integrated device manufacturers, and it is pivotal to the preservation of the foundry-fabless model.

Electrical DFM solutions offer a wealth of yet-untapped benefits.

As we move into 65nm, parametric failures?i.e. chips that fail to meet power and timing requirements?become the dominant yield-limiting mechanism. Parametric yield loss continues to become increasingly significant at the 45nm node and beyond. In this context, there are many opportunities for DFM technology to bridge design and process, and to deliver high-value equivalent-scaling advances.

The manufacturability and yield wins due to previous-generation "geometric DFM" or "shape-centric DFM" tools are already baked into canonical yield ramp methodologies. Now "electrical DFM" solutions offer the greatest untapped potential, with opportunities for double-digit percentage gains in parametric yield.

Electrical DFM is about optimizing objectives that the designer or product engineer cares about: leakage power, dynamic power, timing, timing and power variability, process window and even reliability. The driver for such optimization consists of analysis engines that comprehend a full spectrum of physical and electrical implications of manufacturing. Finally, the "knobs" or degrees of freedom to achieve the optimization goals include changes to placement, wiring and vias?even the dimensions of individual transistors.

In the near future, electrical DFM technologies will be deployed further and further up into the design implementation flow. Ultimately, end customers will be afforded a true "design-for-value" capability, maximizing profit per wafer.

Electrical DFM solutions are built upon three fundamental precepts: drive design requirements into manufacturing; bring manufacturing awareness into design; and work within existing design environments without requiring major changes to the design flow, design signoff, handoff to manufacturing or the fab equipment line.

Design-specific info
Electrical DFM solutions take into account design-specific information; other approaches do not. As a simple example, the actual printed dimension of a feature, such as a transistor gate, will vary through stepper defocus, depending on the feature's pattern environment.

When isolated in a sparse area (iso), a device's printed dimension will differ from that of a device that occurs in a dense area (dense) surrounded by other devices. Without such context information, it cannot be determined whether the line width will vary in the positive or negative direction. The direction of parametric variation clearly depends on the "isoness" or "denseness" of the line's pitch environment. Pattern-context-aware electrical DFM solutions can use this information to drive manufacturing so that the line widths are printed with the intended dimensions.

A small increase in transistor gate length delivers a large reduction in leakage power and variability.

Two critical factors
At 65nm, the most critical factor affecting parametric yield is leakage power, which can represent over 50 percent of the total chip power consumption. At 45nm, leakage power may rise to as much as 60 percent of total power. Furthermore, design techniques used to control leakage at 65nm may run out of steam at 45nm because of the lower supply voltages. At 45nm, triple-Vt technologies may become less viable.

Electrical DFM solutions to the twin challenges of leakage power and variability include techniques such as transistor gate-length biasing. Transistor gate-length biasing offers significant leakage reductions at 65nm and is projected to offer even greater savings at 45nm. Positively biasing the gate lengths of transistors that are not setup-critical has been shown to yield significant dividends in leakage reduction, lower leakage variability and overall higher parametric yield.

Techniques such as this would not be possible with a purely design-centric or a purely manufacturing-centric point of view. Chip designers might be surprised to learn that their power and timing requirements can be used to tailor a manufacturing line for each individual design?indeed, each individual transistor of each individual design?without making any changes or adjustments to the fab equipment line. Chip designers can take advantage of available entitlement or process margin so that the process delivers significantly improved silicon parametric quality.

DFM offers the EDA and IC industries a new opportunity. It requires foundries and their customers to come together in new ways that can lead to new and healthier business models.

If DFM can deliver equivalent scaling and cost reductions up to its potential?and if it can recapture what the past design-manufacturing interface has left on the table?one can reasonably see DFM fueling a future multibillion-dollar market.

This is the road by which design technology?after spending decades in the shadow of process technology?can emerge as the key technology driver for the IC and electronics ecosystem.

- Jacob Jacobson
CEO

- Andrew Kahng
Chairman and co-founder
Blaze DFM Inc.




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