Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Interface
?
?
Interface??

PLL-based clock generators deliver sub-ps jitter

Posted: 19 Mar 2007 ?? ?Print Version ?Bookmark and Share

Keywords:CMOS? clock generator? Fibre Channel? serial ATA? ON Semi?

Clock generation devices from ON Semi

ON Semiconductor has announced the expansion of its high-performance clock generation portfolio with the introduction of PureEdge, a new family of PLL-based devices that deliver 50 percent better phase jitter than competitive products.

Fibre Channel, SATA apps
The first devices in this new familythe NB3N3001 and NB3N3011create LVPECL, sub-picosecond jitter quality clocks at 100 -, 106.25- and 212.5MHz, making them suitable for Fibre Channel and serial ATA applications. This improves timing accuracy, increases design flexibility and lowers cost, making them suitable for high-performance telecom, networking and consumer applications.

The NB3N3001 uses an inexpensive reference crystal to generate a differential LVPECL output clock at 106.25MHz or 212.5MHz. It provides a typical rms phase jitter of less than 0.3ps and noise floor of -135dBc/Hz at 100kHz offset from the carrier frequency.

The NB3N3011 uses an inexpensive reference crystal to generate a differential LVPECL clock signal of 100MHz or 106.25MHz. It provides a typical rms phase jitter of less than 0.3ps and noise floor of -135dBc/Hz at 100 kHz offset from the carrier frequency.

?Growing our timing business is a key focus for the Standard Products Group,? said Dan Huettl, general manager of the advanced logic division at ON Semi. ?We?ve leveraged our EClinPS design with high-speed, low jitter differential signaling techniques and now have the PLL-based low phase noise clock generation technology. With the planned expansion of the PureEdge family, we will continue to gain momentum as a player in the clock generation market space as a provider of solutions for the entire clock tree.?

0.25?m CMOS tech
PureEdge devices are 3.3V clock generators with LVPECL differential outputs. Employing 0.25?m CMOS technology, these devices outperform competitive devices with phase noise comparable to expensive SAW crystal oscillators.

Packaged in a Pb-free TSSOP-8 package, the NB3N3001 and NB3N3011 are priced at $1.50 per unit in 2,500-unit quantities.




Article Comments - PLL-based clock generators deliver s...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top