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Four- and six-layer, high-speed PCB design for the Spartan-3E FT256 BGA package

Posted: 12 Mar 2007 ?? ?Print Version ?Bookmark and Share

Keywords:PCB layout? Spartan-3E? FPGA? signal integrity? Spartan-3E?

Four- and six-layer, high-speed PCB design for the Spartan-3E FT256 BGA package

This application note addresses low-cost, four- to six-layer, high-volume PCB layout for a Spartan-3E FPGA in the FT256 1mm BGA package. The impact of highspeed signals and signal integrity (SI) considerations for low layer count PCB layouts is also reviewed. This application note is intended for design engineers, managers and PCB layout staff, who are already familiar with SI related design issues. It focuses on the Spartan-3E device in the FT256 package, but the information applies to the equivalent FG256 package, and the general guidelines can be used to optimize board layout for other devices and packages.

View the PDF document for more information.





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