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Reference system: MCH OPB DDR SDRAM with OPB Central DMA

Posted: 02 Apr 2007 ?? ?Print Version ?Bookmark and Share

Keywords:OPB DDR SDRAM? OPB Central DMA? MicroBlaze parameters?

This application note describes how to set up MicroBlaze parameters for caching, the clocking structure for the MCH OPB DDR SDRAM, and parameters for OPB burst transactions from the OPB Central DMA controller. This reference system is targeted for the Xilinx SP305 Spartan-3 development board.

View the PDF document for more information.




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