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Next-gen chips bridge design, process

Posted: 02 Apr 2007 ?? ?Print Version ?Bookmark and Share

Keywords:thermoelectric power generator? autonomous power generator? consumer electronic market?

TSMC's Chang: To succeed, design and fab teams must work together.

Taiwan Semiconductor Manufacturing Co. Ltd founding chairman Morris Chang, in his keynote address at last February's International Solid-State Circuits Conference (ISSCC), discussed the strategies foundries need to develop in order to remain profitable in the consumer electronics era.

Chang contends that "annual revenue growth of the semiconductor industry as a whole has slowed since 2000, from 16 percent to where the rate will be closer to 6 percent for 2000 to 2010." Fierce competition has forced many foundries to compete on the basis of price alone, he says, even though their services differ substantially.

"We believe," Chang continues, "that the foundry industry must respond to these challenges by two means: by expanding into new IC product markets enabled by the cost reduction and performance increases resulting from technology scaling; and by penetrating segments of the IC market that are currently not involved in foundry relationships, by broadening the range of technologies that are offered."

Future circuit designers can expect to be able to access process technologies that are tuned in various ways: for memory, analog, high-performance logic or image-sensor applications, as well as for CMOS logic, he says.

Foundries that wish to succeed must develop strategies to avoid commoditization, Chang says. He calls for a deeper and broader relationship between the foundry and each of its customers, saying, "This new type of integrated relationship differs from many previous foundry-customer relationships, in that both design and technology engineering proceed concurrently from an early stage in the product development effort." For the relationship to succeed, there must be a much greater information flow between the design and foundry teams, as well as optimization of both design and process technology to meet product requirements, he says.

Circuit concept development
Meanwhile, technical papers at ISSCC focusing on advances in circuit concepts and systems discussed the interrelationships among high-performance, low-power ICs that already bridge design and process disciplines.

Some of these papers presented "a couple of firsts in system architectures and a couple of lowest-power developments," noted Anantha Chandrakasan, director of the Massachusetts Institute of Technology's Microsystems Technology Labs, who chairs ISSCC's Technology Directions subcommittee.

"There is a need for energy-autonomous devices operating with energy scavenged from the environment for use in wireless sensor networks, RFID tags, health-monitoring systems and ambient intelligence applications," said Chandrakasan.

To that end, researchers at France-based CEA/Leti came up with an architecture for a modular IC that enables thermal energy to be harvested and power stored in the microwatt range. The autonomous power generator unit includes two micropower sources and an associated management IC. On board the circuit, a 1V miniature thermogenerator and RF power receiver are combined with a DC/DC converter, power supply manager and microbattery charger, and a 5nW discharge monitor, to manage and store the harvested energy. A microbattery is deposited above the IC in a 30mm? space.

Microsystem architecture unit is powered by two sources.

Thermoelectric power generators have three main advantages: No human intervention is required throughout their lifetime; they are highly reliable and quiet, since there are no moving mechanical parts; and the materials used are environmentally friendly. The current prototype microgenerator has an output power of 4mW/cm?/C and generates 1V for a temperature difference of 60C. Next, the project members aim to integrate the circuits into one monolithic chip.

Minimum energy
Meanwhile, researchers at MIT have developed an energy-minimization loop, with on-chip energy sensor circuitry, that can dynamically track the minimum-energy operating voltage of a digital circuit under changing workload and operating conditions. The 0.05mm? chip has been processed in 65nm CMOS. The DC/DC converter that enables this minimum-energy operation can deliver load voltages as low as 250mV. And it can achieve over 80 percent efficiency while delivering load powers on the order of 1?W and higher from a 1.2V supply, according to Chandrakasan.

Among the low-power achievements highlighted were three from researchers at Italy's University of Bologna, Japan's University of Tokyo and Belgium's Interuniversity Microelectronics Center (IMEC).

Researchers from the University of Bologna have teamed up with staff from STMicroelectronics in Italy and Fraunhofer IZM in Germany to describe the 3D integration of chips using a wireless (contactless) interconnection scheme based on capacitive coupling. The chips are implemented in 0.13?m CMOS and assembled face-to-face. The chips' receiver and transmission circuits are connected by eight 8?m? electrodes. This enables the vertical propagation of a clock at 1.7GHz, a propagation delay of 420ps for general-purpose signals, and throughput of more than 22Mbps/?m? with energy consumption of 0.08pJ/bit.

Japan effort
For their part, groups at Japan's Keio University and the University of Tokyo have developed a 90nm CMOS transceiver for inductive coupling. At a data rate of 1Gbps, its overall energy dissipation is 20 times lower than anything previously published. The transmitter's energy is 0.11pJ/bit, and the receiver's energy is 0.03pJ/bit.

Researchers from IMEC presented a paper on energy-scalable architectures and circuits for SDRs. They described a performance/energy manager that realizes low-power operation by dynamically exploiting the energy requirements of the application and the environment in which it is located. The transmitter is said to achieve a system-level energy efficiency improvement of up to 40 percent.

Researchers at three entitiesLuxtera, OEwaves and Forza Silicon, all U.S.-basedwere able to able to keep RF power consumption to less than 800mW on a mostly integrated 10.2GHz optoelectronic oscillator. The chip was built using a silicon-photonics monolithic integration technology with a standard 0.13?m SOI CMOS process.

- Nicolas Mokhoff
EE Times

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