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Atheros designs Bluetooth IC for laptops

Posted: 02 Apr 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Bluetooth? networking chip? CMOS process? WLAN?

WLAN chip vendor Atheros Communications Inc. is expanding into Bluetooth with a single-chip offering tuned for PCs. Atheros hopes to bundle the chip with its WLAN solutions to push into laptops.

Betting on growing OEM interest in Bluetooth connectivity for notebook PCs, the company designed the AR3011 to comply with the soon-to-be-ratified Bluetooth 2.1 + enhanced data rate specification. The chip's selling points include an integrated interface that allows for better coexistence with a WLAN and a design that considered the PC from the get-go.

Competing approaches "are all repurposed handset solutions that are targeting the PC. We have optimized our chip. For instance, there is enough SRAM built in that we do not require any external flash. That enables cost and size savings," said Srinivas Pattamatta, senior product-marketing manager in the mobile and embedded division of Atheros.

Atheros cites data from IMS Research to estimate that 31 percent of laptops now come with Bluetooth capability and that 74 percent will have it by 2011. With that in mind, at the beginning of last year, Atheros started hiring engineers with years of Bluetooth experience, including some who helped devise the original spec.

Device details
The AR3011's on-chip memory includes 32Kbytes of data RAM and 256Kbytes of code RAM. The chip was designed in a 0.13?m CMOS process and comes in a 6-by-6mm QFN.

Because the AR3011 can tolerate a healthy amount of power spikes in the system, there are only six external passive components, such as capacitors and resistors, and there is no need for a balun and matching network. The chip also features a USB 2.0 device interface, dual 1.2V voltage regulators, a 32bit CPU and support for Microsoft Vista.

Atheros has not disclosed pricing, but it claims the design promises a 60 percent reduction in component count compared with competitors' chips, for a BOM savings of about 20 percent.

For the software, Atheros worked with another design house, which Pattamatta declined to identify. He said engineers augmented the code to optimize for latency and bootup during a PC startup cycle, but details were not available.

The chip also offers two-, three- and four-wire TDM coexistence support for colocation with a WLAN chipset. Pattamatta said that other algorithm enhancements were made to improve range and minimize interference when operating in tandem with WLANs.

"If you own both pieces of silicon, you can do some clever things," he said. "The standard will provide you with a good level of coexistence when you are 50m away from the access point. As you start going to the fringes, like 100m, that is when you start to need some special algorithmsand that is what we are working on."

- Mike Clendenin
EE Times

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