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Synopsys design platforms support UPF 1.0

Posted: 02 Apr 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Unified Power Format? UPF 1.0? low-power design flow?

Synopsys Inc. has announced a low-power design flow that will implement the Accellera Unified Power Format (UPF) version 1.0 in its IC verification and implementation products in the second half of 2007.

Synopsys is enhancing its Discovery verification platform, its Galaxy design platform, and its DesignWare intellectual property (IP) to support UPF 1.0. The company claims to offer a complete low-power solution today that's proven by over 20 successful multivoltage tapeouts, spanning the entire design flow from system-level tradeoffs to a complete RTL-to-GDSII implementation and signoff.

Synopsys claims that Discovery provides power-aware simulation and equivalence checking, and static analysis of designs that use multiple power domains, level shifters, isolation cells and retention memory. Galaxy claims to implement multivoltage and MTCMOS power gating, clock gating, multi-threshold libraries and dynamic and leakage power optimization.

"Synopsys' entire solution will support UPF in the second half of 2007," said Rich Goldman, VP of strategic market development at Synopsys. "This is important since it enables designers to take advantage of Synopsys' complete and tapeout-proven low power solution, using an open industry standard approved by a majority of the EDA industry for interoperability."

- Richard Goering
EE Times




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